18153601. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Yeonho Jang of Goyang-si (KR)

Jongyoun Kim of Seoul (KR)

Jungho Park of Cheonan-si (KR)

Jaegwon Jang of Hwaseong-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18153601 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The abstract describes a semiconductor package that includes a semiconductor chip, a redistribution insulating layer, an external connection bump, a lower bump pad, and a redistribution pattern.

• The semiconductor package includes a semiconductor chip and a redistribution insulating layer with an opening.
• An external connection bump is present, which has a part that fits into the opening of the redistribution insulating layer.
• A lower bump pad is included, which has a surface in contact with the first part of the external connection bump and another surface opposite to it.
• The first surface of the lower bump pad and the redistribution insulating layer partially overlap.
• A redistribution pattern is used to electrically connect the lower bump pad to the semiconductor chip.

Potential applications of this technology:

• Semiconductor packaging industry
• Electronics manufacturing

Problems solved by this technology:

• Provides a method for electrically connecting a lower bump pad to a semiconductor chip in a semiconductor package.
• Ensures proper alignment and contact between the lower bump pad and the external connection bump.

Benefits of this technology:

• Improved electrical connectivity in semiconductor packages.
• Enhanced reliability and performance of semiconductor devices.

Original Abstract Submitted

A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.