17711705. Semiconductor Device And Method Of Manufacturing The Same simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
Semiconductor Device And Method Of Manufacturing The Same
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Ching-Hung Kao of Tainan City (TW)
Semiconductor Device And Method Of Manufacturing The Same - A simplified explanation of the abstract
This abstract first appeared for US patent application 17711705 titled 'Semiconductor Device And Method Of Manufacturing The Same
Simplified Explanation
The patent application describes a semiconductor device and a method of manufacturing it. The device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, and three elongated vias connected to the interconnect structure. There is also a pad that lands on the three vias.
- The semiconductor device has an interconnect structure on a substrate.
- A passivation layer is placed on top of the interconnect structure.
- Three elongated vias are created in the passivation layer and connected to the interconnect structure.
- The vias are oriented along a first direction.
- A pad is placed on top of the vias, also oriented along the first direction.
Potential applications of this technology:
- Integrated circuits and microchips
- Electronic devices such as smartphones, tablets, and computers
- Communication systems and network devices
Problems solved by this technology:
- Improved interconnectivity and signal transmission within a semiconductor device
- Enhanced reliability and performance of electronic devices
- Reduction in size and complexity of circuitry
Benefits of this technology:
- Increased efficiency and speed of data transfer
- Enhanced functionality and capabilities of electronic devices
- Cost-effective manufacturing process for semiconductor devices
Original Abstract Submitted
A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.
