17814828. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Jong Ho Park of Cheonan-si (KR)
Gyu Ho Kang of Cheonan-si (KR)
Seong-Hoon Bae of Cheonan-si (KR)
Ju-Il Choi of Seongnam-si (KR)
Atsushi Fujisaki of Seongnam-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17814828 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor package that includes a wiring structure, a semiconductor chip, an interposer, a recess, a bonded element, and a mold layer.
- The wiring structure consists of an insulating layer and a conductive pattern.
- The semiconductor chip is placed on the wiring structure.
- The interposer includes another insulating layer and a conductive pattern, with a recess exposing a portion of the insulating layer.
- A bonded element is attached to the interposer inside the recess, facing the semiconductor chip.
- A mold layer covers both the semiconductor chip and the bonded element.
Potential applications of this technology:
- Semiconductor packaging for various electronic devices such as smartphones, computers, and IoT devices.
- Integration of multiple semiconductor chips in a compact and efficient manner.
Problems solved by this technology:
- Provides a reliable and efficient method for packaging semiconductor chips.
- Enables better thermal management and electrical connectivity.
Benefits of this technology:
- Improved performance and reliability of electronic devices.
- Enhanced thermal dissipation for better chip cooling.
- Compact and space-saving design for smaller and thinner devices.
Original Abstract Submitted
A semiconductor package includes a wiring structure that includes a first insulating layer and a first conductive pattern inside the first insulating layer, a first semiconductor chip disposed on the wiring structure, an interposer that includes a second insulating layer, a second conductive pattern inside the second insulating layer, and a recess that includes a first sidewall formed on a first surface of the interposer that faces the first semiconductor chip and a first bottom surface connected with the first sidewall, where the recess exposes at least a portion of the second insulating layer, a first element bonded to the interposer and that faces the first semiconductor chip inside the recess, and a mold layer that covers the first semiconductor chip and the first element.
