17850811. INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Jung-Hung Chang of Hsinchu (TW)

Zhi-Chang Lin of Hsinchu (TW)

Shih-Cheng Chen of Hsinchu (TW)

Tsung-Han Chuang of Hsinchu (TW)

Kuo-Cheng Chiang of Hsinchu (TW)

Chih-Hao Wang of Hsinchu (TW)

INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17850811 titled 'INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS

Simplified Explanation

The abstract describes an integrated circuit that includes a nanostructure transistor with semiconductor nanostructures and a source/drain region. The circuit also includes a fin sidewall spacer and a bottom isolation structure.

• The integrated circuit includes a nanostructure transistor with multiple semiconductor nanostructures and a source/drain region.
• A fin sidewall spacer is used to laterally bound a lower portion of the source/drain region.
• A bottom isolation structure is included to electrically isolate the source/drain region from the semiconductor substrate.

Potential Applications

• This technology can be used in various electronic devices that require integrated circuits, such as smartphones, computers, and IoT devices.
• It can be applied in the development of advanced processors, memory chips, and other high-performance computing components.

Problems Solved

• The integration of nanostructure transistors with semiconductor nanostructures helps to improve the performance and efficiency of integrated circuits.
• The use of a fin sidewall spacer and bottom isolation structure helps to enhance the electrical isolation and reduce leakage current in the circuit.

Benefits

• The integrated circuit with nanostructure transistors provides improved performance and efficiency compared to traditional transistors.
• The use of fin sidewall spacers and bottom isolation structures helps to minimize electrical interference and leakage, leading to better overall circuit performance.

Original Abstract Submitted

An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.