17838246. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chin-Ta Chen of Hsinchu City (TW)

Han-Wei Wu of Tainan City (TW)

Yuan-Hsiang Lung of Hsinchu City (TW)

Hua-Tai Lin of Hsinchu City (TW)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17838246 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The patent application describes a method for forming metal vias in a semiconductor substrate. Here are the key points:

• A dielectric layer is deposited over the semiconductor substrate.
• A first photoresist layer is formed over the dielectric layer.
• The first photoresist layer is patterned to create through holes.
• The height of the first photoresist layer varies between different through holes.
• A spacer is formed on the lower portion of the first photoresist layer.
• An etching process is performed on the dielectric layer to create via holes, with the spacer protecting the lower portion of the first photoresist layer.
• Metal vias are formed in the via holes.

Potential applications of this technology:

• Integrated circuits manufacturing
• Semiconductor device fabrication

Problems solved by this technology:

• Efficient formation of metal vias in a semiconductor substrate
• Improved control over the height of the first photoresist layer

Benefits of this technology:

• Enhanced precision and accuracy in the formation of metal vias
• Cost-effective manufacturing process for integrated circuits
• Improved performance and reliability of semiconductor devices.

Original Abstract Submitted

A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.