17825383. INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Ching-Yu Huang of Hsinchu City (TW)

Wei-Cheng Tzeng of Taipei City (TW)

Shih-Wei Peng of Hsinchu City (TW)

Wei-Cheng Lin of Taichung City (TW)

Jiann-Tyng Tzeng of Hsinchu City (TW)

INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17825383 titled 'INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME

Simplified Explanation

The patent application describes a method for designing and manufacturing integrated circuits. Here are the key points:

• The method involves identifying contact vias in a standard cell, which connect active regions and conductive lines.
• The cell height is calculated based on the width of the active regions.
• Multiple available cell heights are calculated based on the ratio between the widths of the active regions.
• Layout designs of multiple cells are generated based on the calculated cell heights.
• The integrated circuit is manufactured based on the layout designs.

Potential applications of this technology:

• Integrated circuit design and manufacturing
• Semiconductor industry

Problems solved by this technology:

• Efficient design of integrated circuits
• Optimal utilization of available space in the circuit layout

Benefits of this technology:

• Improved performance and functionality of integrated circuits
• Cost-effective design and manufacturing process
• Increased productivity in the semiconductor industry

Original Abstract Submitted

A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.