US Patent Application 18362938. LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS simplified abstract

LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chi-Lin Liu of Hsinchu (TW)

Jerry Chang-Jui Kao of Hsinchu (TW)

Wei-Hsiang Ma of Hsinchu (TW)

Lee-Chung Lu of Hsinchu (TW)

Fong-Yuan Chang of Hsinchu (TW)

Sheng-Hsiung Chen of Hsinchu (TW)

Shang-Chih Hsieh of Hsinchu (TW)

LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18362938 titled 'LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS

Simplified Explanation

The patent application describes a logic circuit that provides a multibit flip-flop function.

• The circuit includes several inverters and a series-chain of 1-bit transfer flip-flop (TXFF) circuits.
• The first inverter generates a clock_bar signal from a clock signal, and the second inverter generates a clock_bar_bar signal from the clock_bar signal.
• The third inverter generates a control_bar signal from a control signal.
• Each TXFF circuit includes a NAND circuit to receive data signals and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q.
• The TGFF circuit also receives inputs from the NAND circuit, the preceding TGFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals.
• The first TXFF circuit in the series-chain receives a start signal instead of the q signal from the preceding TGFF circuit.

Original Abstract Submitted

A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.