View source for US Patent Application 18354820. 2D-Channel Transistor Structure with Source-Drain Engineering simplified abstract

=2D-Channel Transistor Structure with Source-Drain Engineering=


==Organization Name==

[[Taiwan Semiconductor Manufacturing Co., Ltd.]]


==Inventor(s)==

[[Dhanyakumar  Mahaveer Sathaiya of Hsinchu (TW)]]

[[Khaderbad Mrunal Abhijith of Hsinchu City (TW)]]

[[Tzer-Min Shen of Hsinchu City (TW)]]

==2D-Channel Transistor Structure with Source-Drain Engineering - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18354820 titled '2D-Channel Transistor Structure with Source-Drain Engineering

==Simplified Explanation==

- The patent application describes a method for forming semiconductor devices using a two-dimensional (2D) material layer.
- The method involves depositing the 2D material layer over a semiconductor structure and forming a source feature and a drain feature that are electrically connected to the semiconductor structure and the 2D material layer.
- The source feature and drain feature are made of a semiconductor material.
- A gate structure is then formed over the 2D material layer, positioned between the source feature and the drain feature.
- The combination of the gate structure, source feature, drain feature, semiconductor structure, and 2D material layer creates a field-effect transistor.
- The semiconductor structure acts as the first channel, while the 2D material layer acts as the second channel between the source feature and the drain feature.


==Original Abstract Submitted==

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.