View source for US Patent Application 18334590. HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION simplified abstract

=HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION=


==Organization Name==

[[Taiwan Semiconductor Manufacturing Company, Ltd.]]


==Inventor(s)==

[[Tsu Ching Yang of Taipei (TW)]]


[[Feng-Cheng Yang of Zhudong Township (TW)]]


[[Sheng-Chih Lai of Hsinchu County (TW)]]


[[Yu-Wei Jiang of Hsinchu (TW)]]


[[Kuo-Chang Chiang of Hsinchu City (TW)]]


[[Hung-Chang Sun of Kaohsiung City (TW)]]


[[Chen-Jun Wu of Hsinchu City (TW)]]


[[Chung-Te Lin of Tainan City (TW)]]


==HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION - A simplified explanation of the abstract==


*This abstract for appeared for US patent application  number 18334590 Titled 'HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION'

==Simplified Explanation==

The abstract describes a method for creating a memory device. It involves creating stacks of word lines and insulating layers on a semiconductor substrate. A data storage layer and a channel layer are formed on the sidewalls of the word line stacks. An inner insulating layer is then created between the channel layer. An isolation cut process is performed to create an isolation opening, which is filled with an isolation structure made of a second dielectric material. Source/drain openings are formed by etching through the inner insulating layer, and source/drain contacts are created in these openings.


==Original Abstract Submitted==

In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.