View source for US Patent Application 18215907. METHOD AND APPARATUS TO IMPROVE BANDWIDTH EFFICIENCY IN A DYNAMIC RANDOM ACCESS MEMORY simplified abstract

=METHOD AND APPARATUS TO IMPROVE BANDWIDTH EFFICIENCY IN A DYNAMIC RANDOM ACCESS MEMORY=


==Organization Name==

[[Intel Corporation]]


==Inventor(s)==

[[Todd A. Hinck of Arlington MA (US)]]


[[Archhana M of Morgan Hill CA (US)]]


==METHOD AND APPARATUS TO IMPROVE BANDWIDTH EFFICIENCY IN A DYNAMIC RANDOM ACCESS MEMORY - A simplified explanation of the abstract==


*This abstract for appeared for US patent application  number 18215907 Titled 'METHOD AND APPARATUS TO IMPROVE BANDWIDTH EFFICIENCY IN A DYNAMIC RANDOM ACCESS MEMORY'

==Simplified Explanation==

The abstract describes a method to improve the efficiency of accessing data in a type of computer memory called DRAM. The memory array in the DRAM chip is divided into two equal parts, each with multiple banks. Each part is further divided into two equal sub-parts. To access a cache line (a block of data) in the memory array, the first half of the cache line is accessed simultaneously in all the sub-parts. Then, after a certain amount of time, the second half of the cache line is accessed simultaneously in all the sub-parts. This approach helps to reduce the time it takes to access the cache line, thereby improving the overall efficiency of the memory.


==Original Abstract Submitted==

Bandwidth efficiency is improved by reducing time to access a cache line in a DRAM chip. A memory array in the DRAM chip is internally segmented into two equal size portions, each portion having a plurality of banks. Each respective portion is internally segmented into two equal size sub-portions. A cache line in the memory array is accessed by accessing a first half of the cache line in parallel in all of the sub-portions and accessing a second half of the cache line in parallel in all of the sub-portions of the memory array after a gap time.