View source for US Patent Application 17739789. MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS simplified abstract

=MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS=


==Organization Name==

[[Micron Technology, Inc.]]


==Inventor(s)==

[[Pitamber Shukla of Boise ID (US)]]

[[Jiun-Horng Lai of Kanagawa (JP)]]

[[Ching-Huang Lu of Fremont CA (US)]]

[[Fulvio Rori of Boise ID (US)]]

[[Wai Ying Lo of Boise ID (US)]]

[[Scott A. Stoller of Boise ID (US)]]

==MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17739789 titled 'MEMORY SYSTEMS WITH FLEXIBLE ERASE SUSPEND-RESUME OPERATIONS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

==Simplified Explanation==

- The patent application describes memory systems with flexible erase suspend-resume operations.
- The memory device can receive an erase suspend command during an erase operation.
- When the erase suspend command is received, the memory device suspends the erase operation.
- The memory device then resumes the erase operation by ramping the voltage to the flattop level for the second erase pulse.
- Without any erase suspend operations, the memory device can perform a single erase pulse that remains at the flattop voltage for a total duration.
- The total duration of the first and second erase pulses, when combined, is less than or equal to the total duration of the single erase pulse.


==Original Abstract Submitted==

Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.