View source for TEST CIRCUIT IN SCRIBE REGION FOR MEMORY FAILURE ANALYSIS: abstract simplified (17719327)

*This abstract for appeared for patent application  number 17719327 Titled 'TEST CIRCUIT IN SCRIBE REGION FOR MEMORY FAILURE ANALYSIS'

==Simplified Explanation==

The abstract describes the invention of apparatuses and methods that involve a test circuit located in a scribe region between two semiconductor chips. The apparatus includes two adjacent semiconductor chips, with a scribe region between them. The scribe region contains test address pads and an address decoder circuit. The test address pads receive address signals, and the address decoder circuit generates first signals in response to these address signals.


==Original Abstract Submitted==

Apparatuses and methods including a test circuit in a scribe region between chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chip, adjacent to one another; a scribe region between the first and second semiconductor chips; test address pads in the scribe region; and an address decoder circuit in the scribe region. The test address pads receive address signals. The address decoder provides first signals responsive to the address signals from the test address pads.