View source for REVERSED HIGH ASPECT RATIO CONTACT (HARC) STRUCTURE AND PROCESS: abstract simplified (17887203)

*This abstract for appeared for patent application  number 17887203 Titled 'REVERSED HIGH ASPECT RATIO CONTACT (HARC) STRUCTURE AND PROCESS'

==Simplified Explanation==

The abstract describes a semiconductor chip architecture that includes several layers and structures. It starts with a wafer, on which a front-end-of-line (FEOL) layer is located on one side. This FEOL layer consists of a semiconductor device and an interlayer dielectric (ILD) structure on top of the device. The wafer also has a shallow trench isolation (STI) structure. On top of the FEOL layer, there is a middle-of-line (MOL) layer, which includes a contact and a via connected to the contact. An insulating layer is present on the same side of the wafer, adjacent to the via in a horizontal direction. Additionally, there is a power rail that goes through the wafer from the opposite side, and the via extends through the ILD structure, STI structure, and wafer in a vertical direction to make contact with the power rail.


==Original Abstract Submitted==

Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.