View source for Qualcomm incorporated (20240107665). PROVIDING A LOWER INDUCTANCE PATH IN A ROUTING SUBSTRATE FOR A CAPACITOR, AND RELATED ELECTRONIC DEVICES AND FABRICATION METHODS simplified abstract

=PROVIDING A LOWER INDUCTANCE PATH IN A ROUTING SUBSTRATE FOR A CAPACITOR, AND RELATED ELECTRONIC DEVICES AND FABRICATION METHODS=


==Organization Name==

[[:Category:qualcomm incorporated|qualcomm incorporated]]


[[Category:qualcomm incorporated]]

==Inventor(s)==

[[:Category:Biancun Xie of San Diego CA (US)|Biancun Xie of San Diego CA (US)]][[Category:Biancun Xie of San Diego CA (US)]]

[[:Category:Shree Krishna Pandey of San Diego CA (US)|Shree Krishna Pandey of San Diego CA (US)]][[Category:Shree Krishna Pandey of San Diego CA (US)]]

[[:Category:Chin-Kwan Kim of San Diego CA (US)|Chin-Kwan Kim of San Diego CA (US)]][[Category:Chin-Kwan Kim of San Diego CA (US)]]

[[:Category:Ryan Lane of San Diego CA (US)|Ryan Lane of San Diego CA (US)]][[Category:Ryan Lane of San Diego CA (US)]]

[[:Category:Charles David Paynter of Encinitas CA (US)|Charles David Paynter of Encinitas CA (US)]][[Category:Charles David Paynter of Encinitas CA (US)]]

==PROVIDING A LOWER INDUCTANCE PATH IN A ROUTING SUBSTRATE FOR A CAPACITOR, AND RELATED ELECTRONIC DEVICES AND FABRICATION METHODS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240107665 titled 'PROVIDING A LOWER INDUCTANCE PATH IN A ROUTING SUBSTRATE FOR A CAPACITOR, AND RELATED ELECTRONIC DEVICES AND FABRICATION METHODS

==Simplified Explanation==

The patent application describes electronic devices with a routing substrate that provides a lower inductance path for a capacitor, reducing interconnect inductance for improved performance.

* The innovation includes an additional metal layer in the routing substrate, creating a second power plane adjacent to the first power plane for the capacitor.
* This configuration reduces the dielectric thickness between the power planes, lowering interconnect inductance for the capacitor.

== Potential Applications ==
The technology can be applied in high-frequency electronic devices, power distribution systems, and integrated circuits where reducing inductance is critical for performance.

== Problems Solved ==
The innovation addresses the issue of high interconnect inductance in capacitors connected to power distribution networks, improving signal integrity and reducing power losses.

== Benefits ==
The lower inductance path provided by the routing substrate enhances the efficiency and reliability of electronic devices, leading to improved overall performance.

== Potential Commercial Applications ==
This technology can be utilized in telecommunications equipment, data centers, aerospace systems, and other high-performance electronic devices to optimize power distribution and signal integrity.

== Possible Prior Art ==
One possible prior art could be the use of multilayer structures in electronic devices to reduce inductance, but the specific configuration described in this patent application appears to be a novel approach to addressing the issue.

=== Unanswered Questions ===

== How does this technology compare to existing solutions for reducing interconnect inductance in electronic devices? ==
The article does not provide a direct comparison with other methods or technologies currently available in the market.

== What are the potential challenges in implementing this innovation in mass production of electronic devices? ==
The article does not address the practical aspects of scaling up production or potential obstacles in integrating this technology into commercial products.


==Original Abstract Submitted==

electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. in exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. the additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. the disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. this reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.



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