View source for Qualcomm incorporated (20240105762). VERTICALLY INTEGRATED DEVICE STACK INCLUDING SYSTEM ON CHIP AND POWER MANAGEMENT INTEGRATED CIRCUIT simplified abstract

=VERTICALLY INTEGRATED DEVICE STACK INCLUDING SYSTEM ON CHIP AND POWER MANAGEMENT INTEGRATED CIRCUIT=


==Organization Name==

[[:Category:qualcomm incorporated|qualcomm incorporated]]


[[Category:qualcomm incorporated]]

==Inventor(s)==

[[:Category:Peng Zou of Camas WA (US)|Peng Zou of Camas WA (US)]][[Category:Peng Zou of Camas WA (US)]]

[[:Category:Syrus Ziai of Los Altos CA (US)|Syrus Ziai of Los Altos CA (US)]][[Category:Syrus Ziai of Los Altos CA (US)]]

==VERTICALLY INTEGRATED DEVICE STACK INCLUDING SYSTEM ON CHIP AND POWER MANAGEMENT INTEGRATED CIRCUIT - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240105762 titled 'VERTICALLY INTEGRATED DEVICE STACK INCLUDING SYSTEM ON CHIP AND POWER MANAGEMENT INTEGRATED CIRCUIT

==Simplified Explanation==

The semiconductor device described in the patent application consists of a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die arranged in a vertical stack. The SoC die is placed on the first surface of the package substrate, while the PMIC die is attached to the second surface of the package substrate. The PMIC die is connected to the SoC die through via connectors on the package substrate, providing DC power to the SoC die via DC connectors also on the package substrate. The PMIC die includes thin film inductors corresponding to the DC connectors, located on its surface adjacent to the package substrate.

* The semiconductor device includes a package substrate, SoC die, and PMIC die arranged in a vertical stack.
* The PMIC die provides DC power to the SoC die through via connectors and DC connectors on the package substrate.
* Thin film inductors on the PMIC die correspond to the DC connectors and are located near the package substrate.

== Potential Applications ==
The technology described in the patent application could be applied in:
* Mobile devices
* IoT devices
* Wearable technology

== Problems Solved ==
This technology helps in:
* Efficient power management in semiconductor devices
* Compact design for vertical stacking of components

== Benefits ==
The benefits of this technology include:
* Improved power efficiency
* Space-saving design
* Enhanced performance of semiconductor devices

== Potential Commercial Applications ==
The technology could find commercial applications in:
* Consumer electronics
* Automotive industry
* Medical devices

== Possible Prior Art ==
One possible prior art related to this technology is the use of thin film inductors in power management circuits for semiconductor devices. 

== Unanswered Questions ==

=== How does the vertical stacking of components impact the overall performance of the semiconductor device? ===
The vertical stacking of components can potentially affect heat dissipation and signal integrity within the device. Further research and testing may be needed to understand the full implications of this design choice.

=== What are the limitations of using thin film inductors in power management circuits? ===
Thin film inductors may have limitations in terms of power handling capacity and frequency response. It would be essential to investigate these limitations to optimize the performance of the semiconductor device.


==Original Abstract Submitted==

a semiconductor device has a package substrate, a system-on-chip (soc) die, and a power management integrated circuit (pmic) die, arranged in a vertical stack. the soc die is disposed on a first surface of the package substrate, and the pmic die is mechanically coupled to a second surface of the package substrate. the pmic die is electrically coupled to the soc die via first via connectors of the package substrate and configured to provide dc power to the soc die via dc connectors electrically coupled to the via connectors of the package substrate. the pmic die includes thin film inductors, corresponding to the dc connectors, on a surface of the pmic die and located adjacent to the second surface of the package substrate.



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