View source for 20240021614. METHOD TO EMBED PLANAR FETS WITH FINFETS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

=METHOD TO EMBED PLANAR FETS WITH FINFETS=


==Organization Name==

[[:Category:TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.|TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.]]


[[Category:TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.]]

==Inventor(s)==

[[:Category:Harry-Hak-Lay Chuang of Zhubei City (TW)|Harry-Hak-Lay Chuang of Zhubei City (TW)]][[Category:Harry-Hak-Lay Chuang of Zhubei City (TW)]]

[[:Category:Wei Cheng Wu of Zhubei City (TW)|Wei Cheng Wu of Zhubei City (TW)]][[Category:Wei Cheng Wu of Zhubei City (TW)]]

[[:Category:Li-Feng Teng of Hsinchu City (TW)|Li-Feng Teng of Hsinchu City (TW)]][[Category:Li-Feng Teng of Hsinchu City (TW)]]

[[:Category:Li-Jung Liu of Kaohsiung City (TW)|Li-Jung Liu of Kaohsiung City (TW)]][[Category:Li-Jung Liu of Kaohsiung City (TW)]]

==METHOD TO EMBED PLANAR FETS WITH FINFETS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240021614 titled 'METHOD TO EMBED PLANAR FETS WITH FINFETS

==Simplified Explanation==

The present disclosure describes a method for embedding planar field-effect transistors (FETs) with fin field-effect transistors (FinFETs). The method involves patterning a semiconductor substrate to create a mesa and a fin. A trench isolation structure is then formed over the substrate, surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not on the fin. The trench isolation structure is recessed around the fin, but not the mesa. A second gate dielectric layer is deposited over the first gate dielectric layer, covering both the mesa and the fin. A first gate electrode is formed on the mesa, partially defining a planar FET. A second gate electrode is formed on the fin, partially defining a FinFET.

* A method for embedding planar FETs with FinFETs is disclosed.
* The method involves patterning a semiconductor substrate to create a mesa and a fin.
* A trench isolation structure is formed over the substrate, surrounding the mesa and the fin.
* A first gate dielectric layer is formed on the mesa, but not on the fin.
* The trench isolation structure is recessed around the fin, but not the mesa.
* A second gate dielectric layer is deposited over the first gate dielectric layer, covering both the mesa and the fin.
* A first gate electrode is formed on the mesa, partially defining a planar FET.
* A second gate electrode is formed on the fin, partially defining a FinFET.

== Potential Applications ==
* This technology can be used in the manufacturing of integrated circuits.
* It can be applied in the development of advanced semiconductor devices.

== Problems Solved ==
* The method solves the problem of embedding planar FETs with FinFETs in a semiconductor substrate.
* It addresses the challenge of forming gate dielectric layers on both the mesa and the fin.

== Benefits ==
* The method allows for the integration of planar FETs and FinFETs in a single device.
* It enables improved performance and functionality of semiconductor devices.
* The technology offers enhanced control over the electrical properties of the embedded transistors.


==Original Abstract Submitted==

various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (fets) with fin field-effect transistors (finfets). a semiconductor substrate is patterned to define a mesa and a fin. a trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. a first gate dielectric layer is formed on the mesa, but not the fin. the trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. a second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. a first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar fet. a second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finfet.



[[Category:H01L27/088]]
[[Category:H01L29/06]]
[[Category:H01L29/417]]