View source for 18364490. MEMORY DEVICE AND ZQ CALIBRATION METHOD simplified abstract (Changxin Memory Technologies, Inc.)

=MEMORY DEVICE AND ZQ CALIBRATION METHOD=


==Organization Name==

[[:Category:Changxin Memory Technologies, Inc.|Changxin Memory Technologies, Inc.]]


[[Category:Changxin Memory Technologies, Inc.]]

==Inventor(s)==

[[:Category:Kai Tian of Hefei City (CN)|Kai Tian of Hefei City (CN)]][[Category:Kai Tian of Hefei City (CN)]]

==MEMORY DEVICE AND ZQ CALIBRATION METHOD - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18364490 titled 'MEMORY DEVICE AND ZQ CALIBRATION METHOD

==Simplified Explanation==

The present disclosure describes a memory device and a ZQ calibration method. The memory device includes multiple chips connected to a ZQ calibration resistor and an identification module to determine the priority and delay calibration chips.

* The memory device has two calibration resistor interfaces connected to the same ZQ calibration resistor.
* It includes a combination of master and slave chips cascaded together.
* The first and second transmission terminals transmit a ZQ flag signal.
* The identification module identifies the priority calibration chip and the delay calibration chip.
* The primary slave chip is identified as the one cascaded with the priority calibration chip.
* The secondary slave chip is identified as the one cascaded with the delay calibration chip.

==Potential Applications==
* Memory devices in computer systems
* Integrated circuits in electronic devices
* Data storage devices

==Problems Solved==
* Simplifies the ZQ calibration process in memory devices
* Efficient identification of priority and delay calibration chips
* Streamlines the cascading of master and slave chips

==Benefits==
* Improved performance and accuracy of ZQ calibration
* Enhanced reliability and stability of memory devices
* Simplified design and manufacturing process for memory devices


==Original Abstract Submitted==

The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.



[[Category:G11C7/10]]