View source for 18166737. MEMORY DEVICE, MEMORY SYSTEM AND METHOD FOR OPERATING MEMORY SYSTEM simplified abstract (Samsung Electronics Co., Ltd.)

=MEMORY DEVICE, MEMORY SYSTEM AND METHOD FOR OPERATING MEMORY SYSTEM=


==Organization Name==

[[:Category:Samsung Electronics Co., Ltd.|Samsung Electronics Co., Ltd.]]


[[Category:Samsung Electronics Co., Ltd.]]

==Inventor(s)==

[[:Category:Jaehyeok Baek of Suwon-si (KR)|Jaehyeok Baek of Suwon-si (KR)]][[Category:Jaehyeok Baek of Suwon-si (KR)]]

[[:Category:Hye-Ran Kim of Suwon-si (KR)|Hye-Ran Kim of Suwon-si (KR)]][[Category:Hye-Ran Kim of Suwon-si (KR)]]

[[:Category:Min Ho Maeing of Suwon-si (KR)|Min Ho Maeing of Suwon-si (KR)]][[Category:Min Ho Maeing of Suwon-si (KR)]]

[[:Category:SungYong Cho of Suwon-si (KR)|SungYong Cho of Suwon-si (KR)]][[Category:SungYong Cho of Suwon-si (KR)]]

[[:Category:MoonChul Choi of Suwon-si (KR)|MoonChul Choi of Suwon-si (KR)]][[Category:MoonChul Choi of Suwon-si (KR)]]

==MEMORY DEVICE, MEMORY SYSTEM AND METHOD FOR OPERATING MEMORY SYSTEM - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18166737 titled 'MEMORY DEVICE, MEMORY SYSTEM AND METHOD FOR OPERATING MEMORY SYSTEM

==Simplified Explanation==

The patent application describes a memory system that includes a memory device and a memory controller. The memory controller transmits command and address signals as well as a data clock signal to the memory device, and it can also transmit or receive a data signal from the memory device.

* The memory device has a clock distribution network that generates division clock signals for sampling the command and address signal and the data signal.
* The memory device also has a sampler that samples the command and address signal based on the division clock signal.
* Additionally, the memory device has a parity check circuitry that detects and reports any parity errors in the command and address signal.
* The memory controller has processing circuitry that initiates command and address training when a parity error signal is received.

Potential applications of this technology:

* Memory systems in computers, servers, and other electronic devices.
* High-performance data storage systems that require efficient memory access.

Problems solved by this technology:

* Parity errors in the command and address signal can lead to data corruption or system instability. This technology helps detect and address such errors.
* Command and address training can optimize the memory system's performance and reliability.

Benefits of this technology:

* Improved data integrity and system stability by detecting and addressing parity errors.
* Enhanced memory system performance through command and address training.


==Original Abstract Submitted==

Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.



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