View source for 18155906. DIGITALLY CONTROLLED DELAY LINE CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

=DIGITALLY CONTROLLED DELAY LINE CIRCUIT AND METHOD=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Co., Ltd.|Taiwan Semiconductor Manufacturing Co., Ltd.]]


[[Category:Taiwan Semiconductor Manufacturing Co., Ltd.]]

==Inventor(s)==

[[:Category:Chung-Peng Hsieh of Hsinchu (TW)|Chung-Peng Hsieh of Hsinchu (TW)]][[Category:Chung-Peng Hsieh of Hsinchu (TW)]]

[[:Category:Chih-Chiang Chang of Hsinchu (TW)|Chih-Chiang Chang of Hsinchu (TW)]][[Category:Chih-Chiang Chang of Hsinchu (TW)]]

[[:Category:Yung-Chow Peng of Hsinchu (TW)|Yung-Chow Peng of Hsinchu (TW)]][[Category:Yung-Chow Peng of Hsinchu (TW)]]

==DIGITALLY CONTROLLED DELAY LINE CIRCUIT AND METHOD - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18155906 titled 'DIGITALLY CONTROLLED DELAY LINE CIRCUIT AND METHOD

==Simplified Explanation==

The abstract describes a digitally controlled delay line (DCDL) that can propagate a signal from an input terminal to an output terminal with adjustable delay. The DCDL consists of multiple stages that allow the signal to be propagated along different paths.

* The DCDL includes input and output terminals, and multiple stages that propagate a signal along different paths.
* Each stage has three inverters: one for propagating the signal along the first path, one for propagating the signal along the second path, and one for transferring the signal from the first path to the second path.
* The tuning portion of at least one of the inverters includes a combination of parallel, independently controllable p-type transistors and a single independently controllable n-type transistor, or parallel, independently controllable n-type transistors and a single independently controllable p-type transistor.

Potential applications of this technology:

* Communication systems: The DCDL can be used in communication systems to adjust the delay of signals, which can be useful for synchronization or signal processing.
* Data storage: The DCDL can be used in data storage systems to control the timing of data read and write operations.
* Signal processing: The DCDL can be used in various signal processing applications, such as filtering or waveform shaping.

Problems solved by this technology:

* Adjustable delay: The DCDL allows for precise control of signal delay, which can be important in various applications where timing is critical.
* Flexibility: The independently controllable transistors in the tuning portion provide flexibility in adjusting the delay, allowing for customization based on specific requirements.
* Digital control: The DCDL can be digitally controlled, making it easier to integrate into digital systems and allowing for precise and programmable delay adjustments.

Benefits of this technology:

* Improved performance: The DCDL provides a reliable and accurate way to adjust signal delay, leading to improved performance in various applications.
* Cost-effective: The use of digital control and the ability to customize the delay based on specific requirements make the DCDL a cost-effective solution compared to traditional delay line technologies.
* Compact design: The DCDL can be implemented in a compact design, making it suitable for integration into various electronic systems.


==Original Abstract Submitted==

A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.



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