View source for 17957788. UNMATCHED CLOCK FOR COMMAND-ADDRESS AND DATA simplified abstract (ADVANCED MICRO DEVICES, INC.)

=UNMATCHED CLOCK FOR COMMAND-ADDRESS AND DATA=


==Organization Name==

[[:Category:ADVANCED MICRO DEVICES, INC.|ADVANCED MICRO DEVICES, INC.]]


[[Category:ADVANCED MICRO DEVICES, INC.]]

==Inventor(s)==

[[:Category:Aaron D Willey of Hayward CA (US)|Aaron D Willey of Hayward CA (US)]][[Category:Aaron D Willey of Hayward CA (US)]]

[[:Category:Karthik Gopalakrishnan of Cupertino CA (US)|Karthik Gopalakrishnan of Cupertino CA (US)]][[Category:Karthik Gopalakrishnan of Cupertino CA (US)]]

[[:Category:Pradeep Jayaraman of San Jose CA (US)|Pradeep Jayaraman of San Jose CA (US)]][[Category:Pradeep Jayaraman of San Jose CA (US)]]

==UNMATCHED CLOCK FOR COMMAND-ADDRESS AND DATA - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17957788 titled 'UNMATCHED CLOCK FOR COMMAND-ADDRESS AND DATA

==Simplified Explanation==

The abstract describes a memory system with a PHY on an integrated circuit that connects to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit, driver circuits for CA signals, and driver circuits for DQ signals. The DQ signal traces are longer than the clock signal traces to reduce insertion delay.

* The memory system includes a PHY on an integrated circuit.
* The PHY connects to a memory over conductive traces on a substrate.
* The PHY includes a reference clock generation circuit.
* Driver circuits provide CA signals to the memory.
* Driver circuits provide DQ signals to the memory.
* DQ signal traces are longer than clock signal traces to reduce insertion delay.

== Potential Applications ==
This technology could be applied in:
* High-speed memory systems
* Data centers
* Networking equipment

== Problems Solved ==
This technology helps to:
* Reduce insertion delay in memory systems
* Improve signal integrity
* Enhance overall system performance

== Benefits ==
The benefits of this technology include:
* Faster data transfer speeds
* More reliable memory systems
* Improved system efficiency

== Potential Commercial Applications ==
This technology could be commercially applied in:
* Memory module manufacturing
* Computer hardware production
* Telecommunications equipment development

== Possible Prior Art ==
One possible prior art for this technology could be:
* Memory systems with optimized signal routing for reduced delay.

== Unanswered Questions ==

=== How does this technology impact power consumption in memory systems? ===
The abstract does not mention anything about the power consumption implications of this technology.

=== Are there any limitations to the length of the DQ signal traces for reducing insertion delay? ===
The abstract does not provide information on any potential limitations in the length of the DQ signal traces for reducing insertion delay.


==Original Abstract Submitted==

A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing CA signals to the memory, and a second group of driver circuits providing DQ signals to the memory. A plurality of the conductive traces which carry the DQ signals are constructed with a length longer than that of conductive traces carrying the reference clock signal in order to reduce an effective insertion delay associated with coupling the reference clock signal to latch respective incoming DQ signals.



[[Category:G11C11/4076]]