View source for 17957783. MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BRIDGE DIE simplified abstract (Intel Corporation)

=MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BRIDGE DIE=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Jeremy Ecton of Gilbert AZ (US)|Jeremy Ecton of Gilbert AZ (US)]][[Category:Jeremy Ecton of Gilbert AZ (US)]]

[[:Category:Brandon Marin of Gilbert AZ (US)|Brandon Marin of Gilbert AZ (US)]][[Category:Brandon Marin of Gilbert AZ (US)]]

[[:Category:Srinivas Pietambaram of Chandler AZ (US)|Srinivas Pietambaram of Chandler AZ (US)]][[Category:Srinivas Pietambaram of Chandler AZ (US)]]

[[:Category:Hiroki Tanaka of Gilbert AZ (US)|Hiroki Tanaka of Gilbert AZ (US)]][[Category:Hiroki Tanaka of Gilbert AZ (US)]]

[[:Category:Suddhasattwa Nad of Chandler AZ (US)|Suddhasattwa Nad of Chandler AZ (US)]][[Category:Suddhasattwa Nad of Chandler AZ (US)]]

==MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BRIDGE DIE - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17957783 titled 'MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BRIDGE DIE

==Simplified Explanation==

The patent application describes multi-die packages with at least one glass substrate between two adjacent IC dies or surrounding an interconnect bridge die. The IC dies may be placed within recesses in the glass substrate, and conductive vias may extend through the glass substrate. The bridge die can be directly bonded or soldered to the adjacent IC dies for fine pitch interconnect. Metallization features on the second side of the glass substrate electrically interconnect the IC dies to package interconnect interfaces.

* Glass substrate used in multi-die packages
* IC dies placed within recesses in the glass substrate
* Conductive vias extend through the glass substrate
* Bridge die directly bonded or soldered to adjacent IC dies
* Metallization features on glass substrate for electrical interconnect

== Potential Applications ==
The technology described in the patent application could be applied in:
* High-performance computing
* Data centers
* Telecommunications equipment

== Problems Solved ==
The technology addresses the following issues:
* Fine pitch interconnect requirements
* Efficient thermal management
* Enhanced electrical performance

== Benefits ==
The technology offers the following benefits:
* Improved signal integrity
* Higher data transfer speeds
* Enhanced reliability

== Potential Commercial Applications ==
The technology could find commercial applications in:
* Semiconductor industry
* Electronics manufacturing
* Aerospace and defense sector

== Possible Prior Art ==
One possible prior art for this technology could be the use of glass substrates in semiconductor packaging to improve thermal performance and electrical connectivity.

== Unanswered Questions ==
=== How does the technology impact overall package size and weight? ===
The article does not provide information on the potential impact of the technology on the overall size and weight of the package.

=== What are the cost implications of implementing this technology? ===
The article does not discuss the cost implications of incorporating this technology into semiconductor packaging processes.


==Original Abstract Submitted==

Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.



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