View source for 17957483. INTEGRATING DEVICES INTO A CARRIER WAFER FOR THREE DIMENSIONALLY STACKED SEMICONDUCTOR DEVICES simplified abstract (ADVANCED MICRO DEVICES, INC.)

=INTEGRATING DEVICES INTO A CARRIER WAFER FOR THREE DIMENSIONALLY STACKED SEMICONDUCTOR DEVICES=


==Organization Name==

[[:Category:ADVANCED MICRO DEVICES, INC.|ADVANCED MICRO DEVICES, INC.]]


[[Category:ADVANCED MICRO DEVICES, INC.]]

==Inventor(s)==

[[:Category:CHINTAN Buch of SANTA CLARA CA (US)|CHINTAN Buch of SANTA CLARA CA (US)]][[Category:CHINTAN Buch of SANTA CLARA CA (US)]]

[[:Category:RAJA Swaminathan of AUSTIN TX (US)|RAJA Swaminathan of AUSTIN TX (US)]][[Category:RAJA Swaminathan of AUSTIN TX (US)]]

==INTEGRATING DEVICES INTO A CARRIER WAFER FOR THREE DIMENSIONALLY STACKED SEMICONDUCTOR DEVICES - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17957483 titled 'INTEGRATING DEVICES INTO A CARRIER WAFER FOR THREE DIMENSIONALLY STACKED SEMICONDUCTOR DEVICES

==Simplified Explanation==

The method described in the patent application involves forming a semiconductor assembly by coupling a die to a carrier wafer with integrated devices using hybrid bonding, connecting the die to the through-silicon vias and integrated devices, and then coupling a second wafer to the die. A portion of the carrier wafer is removed to reveal a conductive portion of the through-silicon vias.

* Through-silicon vias formed in a carrier wafer with integrated devices
* Die coupled to carrier wafer using hybrid bonding
* Connection tech layers of the die connected to through-silicon vias and integrated devices
* Second wafer coupled to the die
* Removal of portion of carrier wafer to reveal conductive portion of through-silicon vias

== Potential Applications ==
This technology could be applied in the manufacturing of advanced semiconductor devices, such as microprocessors, memory chips, and sensors.

== Problems Solved ==
This technology solves the problem of efficiently connecting dies to carrier wafers with integrated devices, allowing for improved performance and functionality of semiconductor assemblies.

== Benefits ==
The benefits of this technology include enhanced connectivity, increased efficiency in semiconductor assembly manufacturing, and improved overall performance of semiconductor devices.

== Potential Commercial Applications ==
The potential commercial applications of this technology include the production of high-performance electronic devices for various industries, such as telecommunications, automotive, and consumer electronics.

== Possible Prior Art ==
One possible prior art for this technology could be the use of traditional bonding methods in semiconductor assembly manufacturing, which may not provide the same level of connectivity and efficiency as hybrid bonding techniques.

=== Unanswered Questions ===

== How does this technology compare to traditional bonding methods in terms of performance and efficiency? ==
This article does not provide a direct comparison between this technology and traditional bonding methods, leaving the reader to wonder about the specific advantages and disadvantages of each approach.

== What are the specific industries or applications that could benefit the most from this technology? ==
While the article mentions potential applications in various industries, it does not delve into specific examples or case studies, leaving the reader to speculate on the most promising areas for commercialization.


==Original Abstract Submitted==

A method of forming a semiconductor assembly includes forming a set of through-silicon vias in a carrier wafer, where a layer of the carrier wafer includes integrated devices. A die is coupled to a top surface of the carrier wafer including the set of through-silicon vias using hybrid bonding. One or more connection layers of the die are coupled to one or more of the through-silicon vias and coupled to one or more of the integrated devices. A second wafer is coupled to a top surface of the die. An amount is removed from a bottom surface of the carrier wafer that is parallel to and opposite to the top surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon vias.



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