View source for 17937519. PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER simplified abstract (Intel Corporation)

=PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Brandon C. Marin of Gilbert AZ (US)|Brandon C. Marin of Gilbert AZ (US)]][[Category:Brandon C. Marin of Gilbert AZ (US)]]

[[:Category:Gang Duan of Chandler AZ (US)|Gang Duan of Chandler AZ (US)]][[Category:Gang Duan of Chandler AZ (US)]]

[[:Category:Jeremy Ecton of Gilbert AZ (US)|Jeremy Ecton of Gilbert AZ (US)]][[Category:Jeremy Ecton of Gilbert AZ (US)]]

[[:Category:Suddhasattwa Nad of Chandler AZ (US)|Suddhasattwa Nad of Chandler AZ (US)]][[Category:Suddhasattwa Nad of Chandler AZ (US)]]

[[:Category:Srinivas V. Pietambaram of Chandler AZ (US)|Srinivas V. Pietambaram of Chandler AZ (US)]][[Category:Srinivas V. Pietambaram of Chandler AZ (US)]]

==PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17937519 titled 'PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER

==Simplified Explanation==

The patent application describes a microelectronic assembly with an interposer structure of glass, a substrate with organic dielectric material, and multiple IC dies connected through various interconnects.

* Glass interposer structure
* Substrate with organic dielectric material
* IC dies connected through different interconnects
* First IC die connected to substrate with first interconnects
* Second IC die embedded in substrate and connected to first IC die with second interconnects
* Third IC die connected to second side of interposer structure with fourth interconnects

== Potential Applications ==
The technology described in the patent application could be applied in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics.

== Problems Solved ==
This technology solves the problem of efficiently connecting multiple IC dies in a microelectronic assembly while maintaining a compact and reliable structure.

== Benefits ==
The benefits of this technology include improved performance, reduced size, increased reliability, and enhanced functionality of electronic devices.

== Potential Commercial Applications ==
The technology could be used in the manufacturing of advanced electronic devices, leading to more compact and efficient products that meet the demands of modern consumers.

== Possible Prior Art ==
One possible prior art for this technology could be the use of traditional interconnect methods in microelectronic assemblies, which may not be as efficient or reliable as the interconnects described in the patent application.

== Unanswered Questions ==
=== What materials are used for the interconnects in the microelectronic assembly? ===
The patent application does not specify the exact materials used for the interconnects connecting the IC dies in the assembly.

=== How does the embedded IC die in the organic dielectric material affect the overall performance of the microelectronic assembly? ===
The patent application does not provide detailed information on how embedding an IC die in the substrate impacts the performance of the assembly.


==Original Abstract Submitted==

Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.



[[Category:H01L23/498]]
[[Category:H01L21/48]]
[[Category:H01L23/00]]
[[Category:H01L23/14]]
[[Category:H01L23/538]]
[[Category:H01L23/66]]
[[Category:H01L25/065]]