View source for 17936416. VERTICAL INVERTER FORMATION ON STACKED FIELD EFFECT TRANSISTOR (SFET) simplified abstract (International Business Machines Corporation)

=VERTICAL INVERTER FORMATION ON STACKED FIELD EFFECT TRANSISTOR (SFET)=


==Organization Name==

[[:Category:International Business Machines Corporation|International Business Machines Corporation]]


[[Category:International Business Machines Corporation]]

==Inventor(s)==

[[:Category:Min Gyu Sung of Latham NY (US)|Min Gyu Sung of Latham NY (US)]][[Category:Min Gyu Sung of Latham NY (US)]]

[[:Category:Julien Frougier of Albany NY (US)|Julien Frougier of Albany NY (US)]][[Category:Julien Frougier of Albany NY (US)]]

[[:Category:Kangguo Cheng of Schenectady NY (US)|Kangguo Cheng of Schenectady NY (US)]][[Category:Kangguo Cheng of Schenectady NY (US)]]

[[:Category:Ruilong Xie of Niskayuna NY (US)|Ruilong Xie of Niskayuna NY (US)]][[Category:Ruilong Xie of Niskayuna NY (US)]]

[[:Category:Chanro Park of Clifton Park NY (US)|Chanro Park of Clifton Park NY (US)]][[Category:Chanro Park of Clifton Park NY (US)]]

==VERTICAL INVERTER FORMATION ON STACKED FIELD EFFECT TRANSISTOR (SFET) - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17936416 titled 'VERTICAL INVERTER FORMATION ON STACKED FIELD EFFECT TRANSISTOR (SFET)

==Simplified Explanation==

The present invention relates to stacked field effect transistors (SFETs) with integrated vertical inverters. In one embodiment, a first nanosheet is stacked vertically over a second nanosheet, with a common gate formed around a channel region of both nanosheets. The top and bottom source/drain regions are in direct contact with the first and second nanosheets, respectively. Portions of the top and bottom regions are shorted to define a common source/drain region, while other portions are electrically coupled in series through the nanosheets.

* Stacked field effect transistors (SFETs) with integrated vertical inverters
* Vertical stacking of nanosheets with a common gate
* Direct contact of source/drain regions with nanosheets
* Shorting of portions to define a common source/drain region
* Electrical coupling in series through nanosheets

== Potential Applications ==
The technology can be applied in:
* High-performance computing
* Advanced memory devices
* Power management systems

== Problems Solved ==
The technology addresses issues related to:
* Improved transistor performance
* Enhanced integration density
* Reduced power consumption

== Benefits ==
The technology offers benefits such as:
* Increased speed and efficiency
* Higher level of integration
* Lower energy consumption

== Potential Commercial Applications ==
Potential commercial applications include:
* Semiconductor industry
* Electronics manufacturing
* Data storage sector

== Possible Prior Art ==
One possible prior art is the use of traditional field effect transistors (FETs) in integrated circuits for electronic devices.

=== What is the manufacturing process for these SFETs with integrated vertical inverters? ===

The manufacturing process for these SFETs involves stacking nanosheets vertically, forming a common gate around the channel region, and creating direct contact between the source/drain regions and the nanosheets. This process requires precise alignment and control to ensure the proper functioning of the SFETs.

=== How do SFETs with integrated vertical inverters compare to traditional FETs in terms of performance and efficiency? ===

SFETs with integrated vertical inverters offer improved performance and efficiency compared to traditional FETs. The vertical stacking of nanosheets and the integration of inverters allow for higher speed, lower power consumption, and increased integration density in electronic devices.


==Original Abstract Submitted==

Embodiments of the present invention are directed to stacked field effect transistors (SFETs) having integrated vertical inverters. In a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. A common gate is formed around a channel region of the first and second nanosheets. A top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. A first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. A second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.



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