View source for 17933512. ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER simplified abstract (Intel Corporation)

=ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Somnath Kundu of Hillsboro OR (US)|Somnath Kundu of Hillsboro OR (US)]][[Category:Somnath Kundu of Hillsboro OR (US)]]

[[:Category:Amy L. Whitcombe of Saratoga CA (US)|Amy L. Whitcombe of Saratoga CA (US)]][[Category:Amy L. Whitcombe of Saratoga CA (US)]]

[[:Category:Stefano Pellerano of Beaverton OR (US)|Stefano Pellerano of Beaverton OR (US)]][[Category:Stefano Pellerano of Beaverton OR (US)]]

[[:Category:Peter Sagazio of Portland OR (US)|Peter Sagazio of Portland OR (US)]][[Category:Peter Sagazio of Portland OR (US)]]

[[:Category:Brent Carlton of Portland OR (US)|Brent Carlton of Portland OR (US)]][[Category:Brent Carlton of Portland OR (US)]]

==ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17933512 titled 'ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

==Simplified Explanation==

The abstract describes an analog-to-digital converter (ADC) with multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs sample a calibration signal with different clock signals to detect phase shifts and calibrate the ADC accordingly.

* The ADC includes multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit.
* Sub-ADCs sample a calibration signal using different clock signals to detect phase shifts.
* The calibration circuit determines mismatches between phase shifts and thresholds to calibrate the ADC.
* The detection circuit samples signals during operation mode to calibrate the ADC based on phase shift mismatches.

== Potential Applications ==
This technology can be applied in:
* High-speed data acquisition systems
* Communication systems
* Radar systems

== Problems Solved ==
* Improves accuracy and precision of analog-to-digital conversion
* Minimizes phase shift errors in the ADC
* Enhances overall performance of the ADC

== Benefits ==
* Higher resolution and accuracy in digital conversion
* Improved signal processing capabilities
* Enhanced reliability and stability in data acquisition systems

== Potential Commercial Applications ==
Optimized for:
* High-speed data acquisition equipment
* Telecommunication infrastructure
* Radar and sensing systems

== Possible Prior Art ==
One possible prior art is the use of time-interleaved ADCs in high-speed data acquisition systems to improve sampling rates and accuracy.

== Unanswered Questions ==

=== How does the calibration circuit determine the phase shift threshold? ===
The abstract mentions a phase shift threshold, but it does not elaborate on how this threshold is determined or set. This information would be crucial in understanding the calibration process of the ADC.

=== What are the specific clock signals used by the sub-ADCs for sampling? ===
The abstract mentions the use of different clock signals by the sub-ADCs, but it does not specify the exact nature or characteristics of these clock signals. Understanding the specifics of these clock signals would provide insight into the calibration mechanism of the ADC.


==Original Abstract Submitted==

An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.



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[[Category:H04B1/40]]