View source for 17895959. CREATING DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY simplified abstract (Micron Technology, Inc.)

=CREATING DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY=


==Organization Name==

[[:Category:Micron Technology, Inc.|Micron Technology, Inc.]]


[[Category:Micron Technology, Inc.]]

==Inventor(s)==

[[:Category:Jiewei Chen of Meridian ID (US)|Jiewei Chen of Meridian ID (US)]][[Category:Jiewei Chen of Meridian ID (US)]]

[[:Category:Mithun Kumar Ramasahayam of Meridian ID (US)|Mithun Kumar Ramasahayam of Meridian ID (US)]][[Category:Mithun Kumar Ramasahayam of Meridian ID (US)]]

[[:Category:Tomoko Ogura Iwasaki of San Jose CA (US)|Tomoko Ogura Iwasaki of San Jose CA (US)]][[Category:Tomoko Ogura Iwasaki of San Jose CA (US)]]

==CREATING DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17895959 titled 'CREATING DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY

==Simplified Explanation==

The patent application describes a system for manufacturing a memory device that includes a memory array and a logic layer above the memory array.

* Memory array consists of memory cells arranged in memory strings along memory array pillars.
* Logic layer consists of latches arranged along logic layer latch pillars.
* Latches store a multi-bit data pattern representing a sequence of bits to be programmed to the memory cells of the memory array.

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### Potential Applications
* Data storage devices
* Computer memory systems
* Embedded systems

### Problems Solved
* Efficient storage and retrieval of data
* Integration of memory and logic functions in a single device
* Enhanced data processing capabilities

### Benefits
* Higher data storage density
* Faster data processing speeds
* Reduced power consumption compared to separate memory and logic devices


==Original Abstract Submitted==

A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.



[[Category:G06F3/06]]