View source for 17879523. MEMORY DEVICE FOR REDUCING TIMING PARAMETERS AND POWER CONSUMPTION FOR INTERNAL PROCESSING OPERATION AND METHOD OF IMPLEMENTING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=MEMORY DEVICE FOR REDUCING TIMING PARAMETERS AND POWER CONSUMPTION FOR INTERNAL PROCESSING OPERATION AND METHOD OF IMPLEMENTING THE SAME=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Sukhan Lee of Seoul (KR)|Sukhan Lee of Seoul (KR)]][[Category:Sukhan Lee of Seoul (KR)]]

[[:Category:Shinhaeng Kang of Suwon-si (KR)|Shinhaeng Kang of Suwon-si (KR)]][[Category:Shinhaeng Kang of Suwon-si (KR)]]

[[:Category:Kyomin Sohn of Yongin-si (KR)|Kyomin Sohn of Yongin-si (KR)]][[Category:Kyomin Sohn of Yongin-si (KR)]]

==MEMORY DEVICE FOR REDUCING TIMING PARAMETERS AND POWER CONSUMPTION FOR INTERNAL PROCESSING OPERATION AND METHOD OF IMPLEMENTING THE SAME - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17879523 titled 'MEMORY DEVICE FOR REDUCING TIMING PARAMETERS AND POWER CONSUMPTION FOR INTERNAL PROCESSING OPERATION AND METHOD OF IMPLEMENTING THE SAME

==Simplified Explanation==

The abstract describes a memory device and method that aim to reduce timing parameters and power consumption for internal processing operations. The memory device includes a memory cell array, a processing-in-memory (PIM) circuit, and a control logic circuit. 

* The memory device reduces timing parameters and power consumption for internal processing operations.
* It includes a memory cell array, a processing-in-memory (PIM) circuit, and a control logic circuit.
* The PIM circuit performs a processing operation, while the control logic circuit controls a normal mode and an internal processing mode.
* In the internal processing mode, the control logic circuit writes the operation result obtained by the PIM circuit in the memory cell array.
* The control logic circuit also provides read data from the memory cell array to the PIM circuit.

Potential applications of this technology:

* This memory device can be used in various electronic devices such as computers, smartphones, and IoT devices.
* It can enhance the performance and efficiency of internal processing operations in these devices.

Problems solved by this technology:

* The memory device reduces timing parameters, which can lead to faster processing operations.
* It also reduces power consumption, resulting in improved energy efficiency.
* By integrating the processing-in-memory circuit, it eliminates the need for data transfer between memory and processing units, reducing latency.

Benefits of this technology:

* Faster processing operations due to reduced timing parameters.
* Improved energy efficiency and reduced power consumption.
* Elimination of data transfer between memory and processing units, reducing latency.


==Original Abstract Submitted==

A memory device for reducing timing parameters and power consumption for an internal processing operation and a method of implementing the same are provided. The memory device includes a memory cell array, a processing-in-memory (PIM) circuit configured to perform a processing operation and a control logic circuit configured to control a normal mode and an internal processing mode. The control logic circuit writes an operation result obtained by the processing operation of the PIM circuit in the internal processing mode in the memory cell array and provides read data read from the memory cell array to the PIM circuit.



[[Category:G06F3/06]]