View source for 17851967. INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE DRAM AND POWER DELIVERY simplified abstract (Intel Corporation)

=INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE DRAM AND POWER DELIVERY=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Abhishek Anil Sharma of Portland OR (US)|Abhishek Anil Sharma of Portland OR (US)]][[Category:Abhishek Anil Sharma of Portland OR (US)]]

[[:Category:Sagar Suthram of Portland OR (US)|Sagar Suthram of Portland OR (US)]][[Category:Sagar Suthram of Portland OR (US)]]

[[:Category:Wilfred Gomes of Portland OR (US)|Wilfred Gomes of Portland OR (US)]][[Category:Wilfred Gomes of Portland OR (US)]]

[[:Category:Tahir Ghani of Portland OR (US)|Tahir Ghani of Portland OR (US)]][[Category:Tahir Ghani of Portland OR (US)]]

[[:Category:Rishabh Mehandru of Portland OR (US)|Rishabh Mehandru of Portland OR (US)]][[Category:Rishabh Mehandru of Portland OR (US)]]

[[:Category:Cory Weber of Hillsboro OR (US)|Cory Weber of Hillsboro OR (US)]][[Category:Cory Weber of Hillsboro OR (US)]]

[[:Category:Anand S. Murthy of Portland OR (US)|Anand S. Murthy of Portland OR (US)]][[Category:Anand S. Murthy of Portland OR (US)]]

==INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE DRAM AND POWER DELIVERY - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17851967 titled 'INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE DRAM AND POWER DELIVERY

==Simplified Explanation==

The patent application describes a structure that combines memory and power delivery in an integrated circuit. The structure includes a front-side structure with nanowire-based transistors and metallization layers, and a backside structure with dynamic random access memory (DRAM) devices.

* The integrated circuit structure includes nanowire-based transistors and DRAM devices.
* The front-side structure contains the nanowire-based transistors and metallization layers.
* The backside structure is located below the nanowire-based transistors and includes the DRAM devices.
* The nanowire-based transistors provide the processing power, while the DRAM devices provide memory storage.
* The combination of memory and power delivery in a single structure improves the efficiency and performance of the integrated circuit.

== Potential Applications ==
* This technology can be used in various electronic devices, such as smartphones, tablets, and computers.
* It can be applied in data centers and servers to enhance their processing and memory capabilities.
* The structure can be utilized in artificial intelligence systems, autonomous vehicles, and other advanced technologies that require high-performance computing and memory.

== Problems Solved ==
* The integration of memory and power delivery in a single structure reduces the need for separate components, saving space and improving efficiency.
* The combination of nanowire-based transistors and DRAM devices enhances the performance and functionality of the integrated circuit.
* The structure addresses the increasing demand for higher processing power and memory capacity in electronic devices.

== Benefits ==
* Improved efficiency and performance due to the integration of memory and power delivery.
* Space-saving design by eliminating the need for separate memory and power components.
* Enhanced processing power and memory capacity for advanced technologies and applications.


==Original Abstract Submitted==

Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.



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