View source for 17851860. TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AND BYPASS MODE, AND INTEGRATED CIRCUIT INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AND BYPASS MODE, AND INTEGRATED CIRCUIT INCLUDING THE SAME=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:GIHA Nam of Hwaseong-si (KR)|GIHA Nam of Hwaseong-si (KR)]][[Category:GIHA Nam of Hwaseong-si (KR)]]

[[:Category:SANGSOON Im of Seoul (KR)|SANGSOON Im of Seoul (KR)]][[Category:SANGSOON Im of Seoul (KR)]]

==TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AND BYPASS MODE, AND INTEGRATED CIRCUIT INCLUDING THE SAME - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17851860 titled 'TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AND BYPASS MODE, AND INTEGRATED CIRCUIT INCLUDING THE SAME

==Simplified Explanation==

The abstract describes a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit includes a multiplexer that can transmit a cell function input to a cell function output in a bypass mode. It also includes a clock gating scheme that can block a clock signal from transmitting to a scan flip-flop to hold a capture procedure.

* The test circuit can test both the integrated circuit core and its external circuit.
* It uses a multiplexer to transmit a cell function input to a cell function output in a bypass mode.
* It includes a clock gating scheme that can block a clock signal from transmitting to a scan flip-flop.
* The clock gating scheme is used to hold a capture procedure during testing.

== Potential Applications ==
* Testing integrated circuit cores
* Testing external circuits of integrated circuit cores

== Problems Solved ==
* Efficient testing of integrated circuit cores and their external circuits
* Simplified transmission of cell function inputs to cell function outputs
* Controlled capture procedure during testing

== Benefits ==
* Improved efficiency in testing integrated circuit cores
* Simplified testing process
* Enhanced control over capture procedures during testing


==Original Abstract Submitted==

Disclosed is a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit may not only transmit a cell function input to a cell function output using only one multiplexer in a bypass mode, may but also use a clock gating scheme capable of blocking a clock signal from transmitting to a scan flip-flop to hold a capture procedure.



[[Category:G01R31/3177]]
[[Category:G01R31/317]]