View source for 17846109. PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING simplified abstract (Intel Corporation)

=PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Sagar Suthram of Portland OR (US)|Sagar Suthram of Portland OR (US)]][[Category:Sagar Suthram of Portland OR (US)]]

[[:Category:Ravindranath Vithal Mahajan of Chandler AZ (US)|Ravindranath Vithal Mahajan of Chandler AZ (US)]][[Category:Ravindranath Vithal Mahajan of Chandler AZ (US)]]

[[:Category:Debendra Mallik of Chandler AZ (US)|Debendra Mallik of Chandler AZ (US)]][[Category:Debendra Mallik of Chandler AZ (US)]]

[[:Category:Omkar G. Karhade of Chandler AZ (US)|Omkar G. Karhade of Chandler AZ (US)]][[Category:Omkar G. Karhade of Chandler AZ (US)]]

[[:Category:Wilfred Gomes of Portland OR (US)|Wilfred Gomes of Portland OR (US)]][[Category:Wilfred Gomes of Portland OR (US)]]

[[:Category:Pushkar Sharad Ranade of San Jose CA (US)|Pushkar Sharad Ranade of San Jose CA (US)]][[Category:Pushkar Sharad Ranade of San Jose CA (US)]]

[[:Category:Abhishek A. Sharma of Hillsboro OR (US)|Abhishek A. Sharma of Hillsboro OR (US)]][[Category:Abhishek A. Sharma of Hillsboro OR (US)]]

[[:Category:Tahir Ghani of Portland OR (US)|Tahir Ghani of Portland OR (US)]][[Category:Tahir Ghani of Portland OR (US)]]

[[:Category:Anand S. Murthy of Portland OR (US)|Anand S. Murthy of Portland OR (US)]][[Category:Anand S. Murthy of Portland OR (US)]]

[[:Category:Nitin A. Deshpande of Chandler AZ (US)|Nitin A. Deshpande of Chandler AZ (US)]][[Category:Nitin A. Deshpande of Chandler AZ (US)]]

==PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17846109 titled 'PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING

==Simplified Explanation==

The abstract describes embodiments of an integrated circuit (IC) die that consist of three regions attached to each other. The first region has a surface, the second region is attached to the first region along a planar interface, and the third region is attached to the second region along another planar interface. The third region has a surface that is coplanar with the surface of the first region. The first and third regions contain multiple layers of conductive traces in a dielectric material, and bond-pads on the surfaces expose portions of these conductive traces.

* The IC die consists of three regions attached to each other.
* The first and third regions have surfaces that are coplanar.
* The conductive traces in the first and third regions are orthogonal to the surfaces.
* Bond-pads on the surfaces expose portions of the conductive traces.

== Potential Applications ==
This technology can be applied in various fields that utilize integrated circuits, such as:

* Electronics manufacturing
* Semiconductor industry
* Consumer electronics
* Telecommunications
* Automotive electronics

== Problems Solved ==
The technology addresses the following problems:

* Integration of multiple regions in an IC die
* Ensuring coplanarity of surfaces in different regions
* Efficient routing of conductive traces in a dielectric material
* Providing exposed bond-pads for connectivity

== Benefits ==
The technology offers several benefits:

* Improved integration of different regions in an IC die
* Enhanced coplanarity of surfaces, facilitating manufacturing processes
* Efficient routing of conductive traces, optimizing circuit design
* Exposed bond-pads for easy connectivity during assembly and testing


==Original Abstract Submitted==

Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.



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