View source for 17730962. STATIC RANDOM-ACCESS MEMORY (SRAM) DEVICE INCLUDING THREE-DIMENSIONAL STACKED (3DS) FIELD-EFFECT TRANSISTOR (FET) AND LAYOUT THEREOF simplified abstract (Samsung Electronics Co., Ltd.)

=STATIC RANDOM-ACCESS MEMORY (SRAM) DEVICE INCLUDING THREE-DIMENSIONAL STACKED (3DS) FIELD-EFFECT TRANSISTOR (FET) AND LAYOUT THEREOF=


==Organization Name==

[[:Category:Samsung Electronics Co., Ltd.|Samsung Electronics Co., Ltd.]]


[[Category:Samsung Electronics Co., Ltd.]]

==Inventor(s)==

[[:Category:Kyungsoo Kim of Hwaseong-si (KR)|Kyungsoo Kim of Hwaseong-si (KR)]][[Category:Kyungsoo Kim of Hwaseong-si (KR)]]

[[:Category:Kyenhee Lee of Seoul (KR)|Kyenhee Lee of Seoul (KR)]][[Category:Kyenhee Lee of Seoul (KR)]]

==STATIC RANDOM-ACCESS MEMORY (SRAM) DEVICE INCLUDING THREE-DIMENSIONAL STACKED (3DS) FIELD-EFFECT TRANSISTOR (FET) AND LAYOUT THEREOF - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17730962 titled 'STATIC RANDOM-ACCESS MEMORY (SRAM) DEVICE INCLUDING THREE-DIMENSIONAL STACKED (3DS) FIELD-EFFECT TRANSISTOR (FET) AND LAYOUT THEREOF

==Simplified Explanation==

The abstract describes a patent application for a static random-access memory (SRAM) device that utilizes a three-dimensional structured (3DS) field-effect transistor (FET) with a minimized planar area and a simple wiring connection structure. The device includes a semiconductor substrate, two fin active regions, and four gates.

* The semiconductor substrate serves as the foundation for the SRAM device.
* The first fin active region extends in one direction on the substrate, while the second fin active region extends in the same direction but is separated from the first region in a perpendicular direction.
* Four gates are present, extending in the perpendicular direction and intersecting either the first or second fin active region.
* Each fin active region consists of a lower layer and an upper layer, with the upper layer only present in the second region.

Potential applications of this technology:

* Memory devices: The SRAM device described in the patent application can be used in various memory applications, such as computer systems, mobile devices, and embedded systems.
* Integrated circuits: The 3DS FET structure can be integrated into various types of integrated circuits, enabling higher performance and more efficient designs.

Problems solved by this technology:

* Minimized planar area: The 3DS FET structure allows for a smaller footprint, making it suitable for applications where space is limited.
* Simplified wiring connection structure: The design of the SRAM device simplifies the wiring connections, reducing complexity and potential manufacturing issues.

Benefits of this technology:

* Improved performance: The 3DS FET structure enhances the performance of the SRAM device, providing faster access times and lower power consumption.
* Space-saving design: The minimized planar area of the device allows for more efficient use of space in electronic systems.
* Manufacturing efficiency: The simplified wiring connection structure reduces the complexity of manufacturing processes, potentially leading to cost savings and improved yield.


==Original Abstract Submitted==

A static random-access memory (SRAM) device including a three-dimensional structured (3DS) field-effect transistor (FET) having a minimized planar area and a simple wiring connection structure includes a semiconductor substrate, a first fin active region extending on the semiconductor substrate in a first direction, a second fin active region extending on the semiconductor substrate in the first direction and apart from the first fin active region in a second direction perpendicular to the first direction, and four gates extending in the second direction and intersecting part of the first fin active region or the second fin active region. Each of the first fin active region and the second fin active region includes a first region in which only a lower layer is arranged and a second region in which an upper layer is arranged on the lower layer.



[[Category:H01L27/11]]