View source for 17547757. DEBUGGING COMMUNICATION AMONG UNITS ON PROCESSOR SIMULATOR simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

=DEBUGGING COMMUNICATION AMONG UNITS ON PROCESSOR SIMULATOR=


==Organization Name==

[[:Category:INTERNATIONAL BUSINESS MACHINES CORPORATION|INTERNATIONAL BUSINESS MACHINES CORPORATION]]


[[Category:INTERNATIONAL BUSINESS MACHINES CORPORATION]]

==Inventor(s)==

[[:Category:Hiroshi Inoue of Tokyo (JP)|Hiroshi Inoue of Tokyo (JP)]][[Category:Hiroshi Inoue of Tokyo (JP)]]

==DEBUGGING COMMUNICATION AMONG UNITS ON PROCESSOR SIMULATOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17547757 titled 'DEBUGGING COMMUNICATION AMONG UNITS ON PROCESSOR SIMULATOR

==Simplified Explanation==

The abstract describes a method for identifying a data transfer mismatch between a sender and a receiver in a software simulator of a hardware processor. The simulator consists of multiple units that communicate with each other using First-In First-Outs (FIFOs). The method involves counting the amount of data the sender writes to the FIFOs and the amount of data the receiver reads from the FIFOs for a specific data transfer. To avoid blocking during FIFO operations, the method includes two steps: 

* The receiver reads dummy data, even if the FIFOs are empty, when attempting to read from the FIFOs.
* The sender discards written data if the FIFOs are full when attempting to write to the FIFOs.

These steps ensure that the sender and receiver can continue their operations without being blocked. The method then identifies any mismatches in the amount of data written by the sender versus the amount of data read by the receiver for the given data transfer.

Potential applications of this technology:

* Software simulators of hardware processors
* Data transfer analysis in communication systems

Problems solved by this technology:

* Identifying data transfer mismatches between sender and receiver
* Avoiding blocking during FIFO operations

Benefits of this technology:

* Efficient data transfer analysis
* Continuous operation without blocking


==Original Abstract Submitted==

A method is provided for identifying a data transfer mismatch between a sender and a receiver from among units of a software simulator of a hardware processor. The simulator runs the plurality of the units which communicate with each other via First-In First-Outs (FIFOs). The method counts amounts of data the sender writes to the FIFOs and the receiver reads from the FIFOs for a given data transfer. The method avoids blocking during FIFO reading and writing operations by (i) reading dummy data by the receiver, even if the FIFOs are empty, when the receiver tries reading from the FIFOs, and (ii) discarding written data if the FIFOs are full, when the sender tries writing to the FIFOs. The method identifies mismatches in the amount of data the sender writes to the FIFOs versus the amount of data the receiver reads from the FIFOs for the given data transfer.



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