View source for 17544993. IN-SITU LOW TEMPERATURE DIELECTRIC DEPOSITION AND SELECTIVE TRIM OF PHASE CHANGE MATERIALS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

=IN-SITU LOW TEMPERATURE DIELECTRIC DEPOSITION AND SELECTIVE TRIM OF PHASE CHANGE MATERIALS=


==Organization Name==

[[:Category:INTERNATIONAL BUSINESS MACHINES CORPORATION|INTERNATIONAL BUSINESS MACHINES CORPORATION]]


[[Category:INTERNATIONAL BUSINESS MACHINES CORPORATION]]

==Inventor(s)==

[[:Category:Luxherta Buzi of Chappaqua NY (US)|Luxherta Buzi of Chappaqua NY (US)]][[Category:Luxherta Buzi of Chappaqua NY (US)]]

[[:Category:HIROYUKI Miyazoe of White Plains NY (US)|HIROYUKI Miyazoe of White Plains NY (US)]][[Category:HIROYUKI Miyazoe of White Plains NY (US)]]

[[:Category:Henry K. Utomo of Ridgefield CT (US)|Henry K. Utomo of Ridgefield CT (US)]][[Category:Henry K. Utomo of Ridgefield CT (US)]]

[[:Category:Matthew Peter Sagianis of Bayside NY (US)|Matthew Peter Sagianis of Bayside NY (US)]][[Category:Matthew Peter Sagianis of Bayside NY (US)]]

==IN-SITU LOW TEMPERATURE DIELECTRIC DEPOSITION AND SELECTIVE TRIM OF PHASE CHANGE MATERIALS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17544993 titled 'IN-SITU LOW TEMPERATURE DIELECTRIC DEPOSITION AND SELECTIVE TRIM OF PHASE CHANGE MATERIALS

==Simplified Explanation==

The patent application describes a method of fabricating a resistive semiconductor memory structure. This method allows for selective etching of phase change materials during the deposition of dielectric at low temperature, all within the same processing chamber.

* The method involves using a semiconductor wafer with a resistive memory device structure that has layers of phase change material.
* The layers of phase change material have oxidized sidewall surfaces due to a prior etching step.
* The method then involves encapsulating the resistive memory device structure by depositing a layer of dielectric material using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) technique.
* During the encapsulating process, the wafer is etched within the processing chamber to selectively remove the oxidation on the sidewall surfaces of the phase change material.

Potential applications of this technology:

* Fabrication of resistive semiconductor memory devices
* Memory storage in electronic devices
* Data storage in computer systems

Problems solved by this technology:

* Selective etching of phase change materials during the deposition of dielectric at low temperature
* Removal of oxidation on the sidewall surfaces of the phase change material

Benefits of this technology:

* Simplified fabrication process by performing etching and encapsulation in the same processing chamber
* Improved control over the selective removal of oxidation on the sidewall surfaces
* Enhanced performance and reliability of resistive semiconductor memory structures.


==Original Abstract Submitted==

A method of fabricating a resistive semiconductor memory structure that provides in-situ selective etch of phase change materials during deposition of dielectric at low temperature (in the same chamber). The method provides, to a single processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form a resistive memory device. The one or more layers of phase change material have oxidized sidewall surfaces as a result of a prior etching step where a whole stack structure of the layers forming the resistive memory structure is etched. Then, an encapsulating of the trimmed resistive memory device structure is performed by depositing, within the processing chamber, using a PECVD, a layer of dielectric material, and during the encapsulating, etching, within the processing chamber, the wafer to selectively remove the phase change material oxidation at the sidewall surfaces.



[[Category:H01L27/24]]
[[Category:C23C16/455]]