View source for 17532572. Synthesizing Zero-Loss Low-Power Approximate DNN Accelerators With Large-Scale Search simplified abstract (GOOGLE LLC)

=Synthesizing Zero-Loss Low-Power Approximate DNN Accelerators With Large-Scale Search=


==Organization Name==

[[:Category:GOOGLE LLC|GOOGLE LLC]]


[[Category:GOOGLE LLC]]

==Inventor(s)==

[[:Category:Azalia Mirhoseini of Mountain View CA (US)|Azalia Mirhoseini of Mountain View CA (US)]][[Category:Azalia Mirhoseini of Mountain View CA (US)]]

[[:Category:Safeen Huda of San Jose CA (US)|Safeen Huda of San Jose CA (US)]][[Category:Safeen Huda of San Jose CA (US)]]

[[:Category:Martin Christoph Maas of Mountain View CA (US)|Martin Christoph Maas of Mountain View CA (US)]][[Category:Martin Christoph Maas of Mountain View CA (US)]]

[[:Category:Paras Jagdish Jain of Cupertino CA (US)|Paras Jagdish Jain of Cupertino CA (US)]][[Category:Paras Jagdish Jain of Cupertino CA (US)]]

[[:Category:Jeffrey Adgate Dean of Palo Alto CA (US)|Jeffrey Adgate Dean of Palo Alto CA (US)]][[Category:Jeffrey Adgate Dean of Palo Alto CA (US)]]

==Synthesizing Zero-Loss Low-Power Approximate DNN Accelerators With Large-Scale Search - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17532572 titled 'Synthesizing Zero-Loss Low-Power Approximate DNN Accelerators With Large-Scale Search

==Simplified Explanation==

The patent application describes a method for designing low-power deep learning accelerator chips that maintain high accuracy in executing deep learning models. Here are the key points:

* The invention focuses on designing approximate systolic arrays, which are key components of deep learning accelerator chips.
* The performance of each approximate systolic array in processing a deep neural network (DNN) is evaluated.
* Each layer of the DNN is assigned to an approximate systolic array based on the evaluation.
* A subset of the approximate systolic arrays is selected for inclusion in the chip design based on the mapping and performance evaluation.

Potential applications of this technology:

* Deep learning accelerator chips can be used in various fields such as computer vision, natural language processing, and robotics.
* The technology can be applied in edge computing devices, enabling efficient and accurate deep learning inference on the device itself.
* It can be used in autonomous vehicles for real-time object detection and recognition.

Problems solved by this technology:

* Deep learning models require significant computational power, which can be a challenge in resource-constrained devices.
* Power consumption is a critical concern for deep learning accelerators, especially in mobile and IoT devices.
* Maintaining accuracy while reducing power consumption is a complex problem in deep learning acceleration.

Benefits of this technology:

* The low-power deep learning accelerator chips designed using this method can provide efficient and accurate inference capabilities.
* By reducing power consumption, the technology enables longer battery life in mobile devices and reduces energy consumption in data centers.
* The method ensures minimal accuracy loss, ensuring reliable and trustworthy deep learning inference results.


==Original Abstract Submitted==

Systems and methods are provided for designing approximate, low-power deep learning accelerator chips that have little to no accuracy loss when executing a deep learning model. A set of approximate systolic arrays may be generated. The performance of each approximate systolic array in the set of approximate systolic arrays processing a deep neural network (DNN) may be determined. Each layer in the DNN may be mapped to an approximate systolic array in the set of approximate systolic arrays. A subset of the set of approximate systolic arrays may be selected for inclusion in the inference chip design based on the mapping and the performance of each approximate systolic array in the set of approximate systolic arrays.



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