SEARCH RESULTS for assignor:"XIE, RUILONG"

Showing 1 to 20 of 68 results

Last Update Patent(s) Assignor(s) Orig. Assignee(s) Assignee(s) Reel/Frame
14-Jun-2018

(X0) 1: AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS

(A1) 2: AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS

PARK, CHANRO

SUNG, MIN GYU

KIM, HOON

XIE, RUILONG

GLOBALFOUNDRIES INC.

40721/32

14-Jun-2018

(X0) 1: SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS

(A1) 2: SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS

CHANEMOUGAME, DANIEL

XIE, RUILONG

LIEBMANN, LARS

GLOBALFOUNDRIES INC.

44710/280

31-May-2018

(X0) 1: SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS

(A1) 2: SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS

XIE, RUILONG

YEH, CHUN-CHEN

GLOBALFOUNDRIES INC.

40431/78

29-May-2018

(X0) 1: REPLACEMENT LOW-K SPACER

(A1) 2: REPLACEMENT LOW-K SPACER

(B2) 9: REPLACEMENT LOW-K SPACER

CAI, XIUYU

XIE, RUILONG

GLOBALFOUNDRIES INC.

41624/678

29-May-2018

(X0) 1: METHODS OF FORMING AN ISOLATED NANO-SHEET TRANSISTOR DEVICE AND THE RESULTING DEVICE

(B1) 9: METHODS OF FORMING AN ISOLATED NANO-SHEET TRANSISTOR DEVICE AND THE RESULTING DEVICE

XIE, RUILONG

CHAO, ROBINHSINKU

CHENG, KANGGUO

ADUSUMILLI, SIVA P.

MONTANINI, PIETRO

GLOBALFOUNDRIES INC.

43024/101

22-May-2018

(X0) 1: FIN PATTERNING FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR

(A1) 2: FIN PATTERNING FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR

(B2) 9: FIN PATTERNING FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR

XIE, RUILONG

SUNG, MIN GYU

CAVE, NIGEL G.

LIEBMANN, LARS

GLOBALFOUNDRIES INC.

39817/591

17-May-2018

(A1) 2: TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA

(X0) 1: TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA

XIE, RUILONG

SUNG, MIN GYU

PARK, CHANRO

LIEBMANN, LARS WOLFGANG

KIM, HOON

GLOBALFOUNDRIES INC.

40327/668

17-May-2018

(X0) 1: FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH

(A1) 2: FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH

CHENG, KANGGUO

YAMASHITA, TENKO

YEH, CHUN-CHEN

XIE, RUILONG

INTERNATIONAL BUSINESS MACHINES CORPORATION

44472/931

15-May-2018

(A1) 2: METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE

(B2) 9: METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE

(X0) 1: METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE

(B1) 9: METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE

BENTLEY, STEVEN

XIE, RUILONG

GLOBALFOUNDRIES INC.

40326/109

10-May-2018

(X0) 1: METHOD TO FORM AIR-GAP SPACERS AND AIR-GAP SPACER-CONTAINING STRUCTURES

(A1) 2: METHOD TO FORM AIR-GAP SPACERS AND AIR-GAP SPACER-CONTAINING STRUCTURES

ZHANG, XUNYUAN

XIE, RUILONG

GLOBALFOUNDRIES INC.

40225/44

10-May-2018

(X0) 1: SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS

(A1) 2: SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS

XIE, RUILONG

SUNG, MIN GYU

PARK, CHANRO

KIM, HOON

GLOBALFOUNDRIES INC.

40245/29

10-May-2018

(X0) 1: METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

(A1) 2: METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

(B2) 9: METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

PARK, CHANRO

BENTLEY, STEVEN

KIM, HOON

XIE, RUILONG

SUNG, MIN GYU

GLOBALFOUNDRIES INC.

40576/238

03-May-2018

(X0) 1: METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE THE ACTIVE REGION AND AN AIR GAP ADJACENT THE GATE OF THE TRANSISTOR

(A1) 2: METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE THE ACTIVE REGION AND AN AIR GAP ADJACENT THE GATE OF THE TRANSISTOR

PARK, CHANRO

XIE, RUILONG

KIM, HOON

SUNG, MIN GYU

GLOBALFOUNDRIES INC.

40159/500

03-May-2018

(X0) 1: INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND ELECTRICAL FUSES

(A1) 2: INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND ELECTRICAL FUSES

XIE, RUILONG

CHENG, KANGGUO

YAMASHITA, TENKO

YEH, CHUN-CHEN

GLOBALFOUNDRIES INC.

40175/819

03-May-2018

(X0) 1: HARD MASK LAYER TO REDUCE LOSS OF ISOLATION MATERIAL DURING DUMMY GATE REMOVAL

(A1) 2: HARD MASK LAYER TO REDUCE LOSS OF ISOLATION MATERIAL DURING DUMMY GATE REMOVAL

XIE, RUILONG

SUNG, MIN GYU

PARK, CHANRO

KIM, HOON

GLOBALFOUNDRIES INC.

40178/363

03-May-2018

(X0) 1: INNER SPACER FOR NANOSHEET TRANSISTORS

(A1) 2: INNER SPACER FOR NANOSHEET TRANSISTORS

CHENG, KANGGUO

XIE, RUILONG

YAMASHITA, TENKO

YEH, CHUN-CHEN

INTERNATIONAL BUSINESS MACHINES CORPORATION

44257/92

03-May-2018

(X0) 1: METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

(A1) 2: METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

KIM, HOON

SUNG, MIN GYU

XIE, RUILONG

PARK, CHANRO

GLOBALFOUNDRIES INC.

44906/489

01-May-2018

(X0) 1: METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING INTEGRATED CIRCUIT STRUCTURE

(B1) 9: METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING INTEGRATED CIRCUIT STRUCTURE

XIE, RUILONG

YEH, CHUN-CHEN

YAMASHITA, TENKO

CHENG, KANGGUO

GLOBALFOUNDRIES INC.

42044/656

01-May-2018

(X0) 1: ULTRA-SCALE GATE CUT PILLAR WITH OVERLAY IMMUNITY AND METHOD FOR PRODUCING THE SAME

(B1) 9: ULTRA-SCALE GATE CUT PILLAR WITH OVERLAY IMMUNITY AND METHOD FOR PRODUCING THE SAME

ZANG, HUI

WATTS, JOSEF

XIE, RUILONG

GLOBALFOUNDRIES INC.

43336/681

26-Apr-2018

(X0) 1: FORMING A CONTACT FOR A SEMICONDUCTOR DEVICE

(A1) 2: FORMING A CONTACT FOR A SEMICONDUCTOR DEVICE

GLUSCHENKOV, OLEG

LIU, ZUOGUANG

MOCHIZUKI, SHOGO

NIIMI, HIROAKI

XIE, RUILONG

INTERNATIONAL BUSINESS MACHINES CORPORATION

41799/83