SEARCH RESULTS for assignor:"XIE, RUILONG"

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(X0) 15477565: METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

(A1) 20180286956: METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

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(X0) 15658835: METHODS OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH GATE CUT ISOLATION REGIONS BETWEEN REPLACEMENT METAL GATES

(B1) 1: METHODS OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH GATE CUT ISOLATION REGIONS BETWEEN REPLACEMENT METAL GATES

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(X0) 15814445: INTEGRATED CIRCUIT STRUCTURE INCORPORATING A STACKED PAIR OF FIELD EFFECT TRANSISTORS AND A BURIED INTERCONNECT AND METHOD

(B1) 1: INTEGRATED CIRCUIT STRUCTURE INCORPORATING A STACKED PAIR OF FIELD EFFECT TRANSISTORS AND A BURIED INTERCONNECT AND METHOD

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(X0) 15986031: UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING

(A1) 20180277648: UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING

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(X0) 15467628: METHODS OF FORMING CONDUCTIVE STRUCTURES

(A1) 20180277426: METHODS OF FORMING CONDUCTIVE STRUCTURES

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(X0) 15469237: REDUCING BENDING IN PARALLEL STRUCTURES IN SEMICONDUCTOR FABRICATION

(A1) 20180277663: REDUCING BENDING IN PARALLEL STRUCTURES IN SEMICONDUCTOR FABRICATION

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(X0) 15469701: METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A GATE CONTACT ABOVE THE ACTIVE REGION OF THE TRANSISTOR

(A1) 20180277430: METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A GATE CONTACT ABOVE THE ACTIVE REGION OF THE TRANSISTOR

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(X0) 15470205: GATE CUTS AFTER METAL GATE FORMATION

(B1) 1: GATE CUTS AFTER METAL GATE FORMATION

(A1) 20180277645: GATE CUTS AFTER METAL GATE FORMATION

(B2) 1: GATE CUTS AFTER METAL GATE FORMATION

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(X0) 15458457: VERTICAL FIELD-EFFECT TRANSISTORS WITH CONTROLLED DIMENSIONS

(A1) 20180269312: VERTICAL FIELD-EFFECT TRANSISTORS WITH CONTROLLED DIMENSIONS

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(X0) 15285092: METHODS OF FORMING METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING PRODUCTS

(A1) 20180096932: METHODS OF FORMING METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING PRODUCTS

(B2) 1: METHODS OF FORMING METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING PRODUCTS

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(X0) 15439575: FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH

(A1) 20170288039: FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH

(B2) 1: FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH

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(X0) 15455313: METHOD FOR FORMING A PROTECTION DEVICE HAVING AN INNER CONTACT SPACER AND THE RESULTING DEVICES

(A1) 20180261595: METHOD FOR FORMING A PROTECTION DEVICE HAVING AN INNER CONTACT SPACER AND THE RESULTING DEVICES

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(X0) 15455203: FIN-TYPE FIELD EFFECT TRANSISTORS (FINFETS) WITH REPLACEMENT METAL GATES AND METHODS

(A1) 20180261514: FIN-TYPE FIELD EFFECT TRANSISTORS (FINFETS) WITH REPLACEMENT METAL GATES AND METHODS

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(X0) 15878486: SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS

(A1) 20180166335: SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS

(B2) 1: SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS

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(X0) 15447210: ETCH-RESISTANT SPACER FORMATION ON GATE STRUCTURE

(A1) 20180254331: ETCH-RESISTANT SPACER FORMATION ON GATE STRUCTURE

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(X0) 15423326: METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE

(A1) 20180218947: METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE

(B2) 1: METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE

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(X0) 14581857: SEMICONDUCTOR DEVICES HAVING LOW CONTACT RESISTANCE AND LOW CURRENT LEAKAGE

(A1) 20160181390: SEMICONDUCTOR DEVICES HAVING LOW CONTACT RESISTANCE AND LOW CURRENT LEAKAGE

(B2) 1: SEMICONDUCTOR DEVICES HAVING LOW CONTACT RESISTANCE AND LOW CURRENT LEAKAGE

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(X0) 15438114: Techniques for VFET Top Source/Drain Epitaxy

(A1) 20180240873: Techniques for VFET Top Source/Drain Epitaxy

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(X0) 15889654: METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS AND THE RESULTING DEVICES

(A1) 20180240715: METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS AND THE RESULTING DEVICES

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(X0) 15955989: AIR-GAP GATE SIDEWALL SPACER AND METHOD

(A1) 20180240883: AIR-GAP GATE SIDEWALL SPACER AND METHOD

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