SEARCH RESULTS for assignor:"PARK, CHANRO"

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(X0) 15477565: METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

(A1) 20180286956: METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

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(X0) 15658835: METHODS OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH GATE CUT ISOLATION REGIONS BETWEEN REPLACEMENT METAL GATES

(B1) 1: METHODS OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH GATE CUT ISOLATION REGIONS BETWEEN REPLACEMENT METAL GATES

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(X0) 15468170: FIELD EFFECT TRANSISTOR (FET) WITH A GATE HAVING A RECESSED WORK FUNCTION METAL LAYER AND METHOD OF FORMING THE FET

(A1) 20180277652: FIELD EFFECT TRANSISTOR (FET) WITH A GATE HAVING A RECESSED WORK FUNCTION METAL LAYER AND METHOD OF FORMING THE FET

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(X0) 15469701: METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A GATE CONTACT ABOVE THE ACTIVE REGION OF THE TRANSISTOR

(A1) 20180277430: METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A GATE CONTACT ABOVE THE ACTIVE REGION OF THE TRANSISTOR

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(X0) 15470205: GATE CUTS AFTER METAL GATE FORMATION

(B1) 1: GATE CUTS AFTER METAL GATE FORMATION

(A1) 20180277645: GATE CUTS AFTER METAL GATE FORMATION

(B2) 1: GATE CUTS AFTER METAL GATE FORMATION

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(X0) 15455203: FIN-TYPE FIELD EFFECT TRANSISTORS (FINFETS) WITH REPLACEMENT METAL GATES AND METHODS

(A1) 20180261514: FIN-TYPE FIELD EFFECT TRANSISTORS (FINFETS) WITH REPLACEMENT METAL GATES AND METHODS

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(X0) 15977437: AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

(A1) 20180261494: AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

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(X0) 15851774: MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT

(A1) 20180182668: MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT

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(X0) 15376831: AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS

(A1) 20180166319: AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS

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(X0) 15443335: DUAL MANDRELS TO ENABLE VARIABLE FIN PITCH

(B1) 9: DUAL MANDRELS TO ENABLE VARIABLE FIN PITCH

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(X0) 15664584: INVERTED DAMASCENE INTERCONNECT STRUCTURES

(B1) 9: INVERTED DAMASCENE INTERCONNECT STRUCTURES

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(A1) 20180138279: TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA

(X0) 15351893: TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA

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(X0) 15345137: SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS

(A1) 20180130889: SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS

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(X0) 15345644: METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

(A1) 20180130895: METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

(B2) 9: METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

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(X0) 15337254: METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE THE ACTIVE REGION AND AN AIR GAP ADJACENT THE GATE OF THE TRANSISTOR

(A1) 20180122919: METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE THE ACTIVE REGION AND AN AIR GAP ADJACENT THE GATE OF THE TRANSISTOR

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(X0) 15339497: HARD MASK LAYER TO REDUCE LOSS OF ISOLATION MATERIAL DURING DUMMY GATE REMOVAL

(A1) 20180122644: HARD MASK LAYER TO REDUCE LOSS OF ISOLATION MATERIAL DURING DUMMY GATE REMOVAL

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(X0) 15846365: METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

(A1) 20180122702: METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES

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(X0) 15600874: METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE AN ACTIVE REGION AND THE RESULTING DEVICE

(B1) 9: METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE AN ACTIVE REGION AND THE RESULTING DEVICE

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(X0) 15657659: METHODS OF FORMING NANOSHEET TRANSISTOR WITH DIELECTRIC ISOLATION OF SOURCE-DRAIN REGIONS AND RELATED STRUCTURE

(B1) 9: METHODS OF FORMING NANOSHEET TRANSISTOR WITH DIELECTRIC ISOLATION OF SOURCE-DRAIN REGIONS AND RELATED STRUCTURE

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(X0) 15284110: PREVENTING OXIDATION DEFECTS IN STRAIN-RELAXED FINS BY REDUCING LOCAL GAP FILL VOIDS

(A1) 20180096895: PREVENTING OXIDATION DEFECTS IN STRAIN-RELAXED FINS BY REDUCING LOCAL GAP FILL VOIDS

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