SEARCH RESULTS for assignor:"MOCHIZUKI, SHOGO"

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(X0) 15466519: VERTICAL TRANSISTOR TOP EPITAXY SOURCE/DRAIN AND CONTACT STRUCTURE

(A1) 20180277445: VERTICAL TRANSISTOR TOP EPITAXY SOURCE/DRAIN AND CONTACT STRUCTURE

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(X0) 15466382: CONTACT FORMATION IN SEMICONDUCTOR DEVICES

(A1) 20180277483: CONTACT FORMATION IN SEMICONDUCTOR DEVICES

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(X0) 15811164: VERTICAL TRANSISTOR TOP EPITAXY SOURCE/DRAIN AND CONTACT STRUCTURE

(A1) 20180277446: VERTICAL TRANSISTOR TOP EPITAXY SOURCE/DRAIN AND CONTACT STRUCTURE

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(X0) 15905885: BOTTOM CONTACT RESISTANCE REDUCTION ON VFET

(B1) 1: BOTTOM CONTACT RESISTANCE REDUCTION ON VFET

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(X0) 15980789: REDUCING RESISTANCE OF BOTTOM SOURCE/DRAIN IN VERTICAL CHANNEL DEVICES

(A1) 20180269310: REDUCING RESISTANCE OF BOTTOM SOURCE/DRAIN IN VERTICAL CHANNEL DEVICES

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(X0) 15626680: SELF ALIGNED TOP EXTENSION FORMATION FOR VERTICAL TRANSISTORS

(A1) 20180114859: SELF ALIGNED TOP EXTENSION FORMATION FOR VERTICAL TRANSISTORS

(B2) 1: SELF ALIGNED TOP EXTENSION FORMATION FOR VERTICAL TRANSISTORS

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(B2) 1: REDUCING RESISTANCE OF BOTTOM SOURCE/DRAIN IN VERTICAL CHANNEL DEVICES

(X0) 15457580: REDUCING RESISTANCE OF BOTTOM SOURCE/DRAIN IN VERTICAL CHANNEL DEVICES

(A1) 20180261685: REDUCING RESISTANCE OF BOTTOM SOURCE/DRAIN IN VERTICAL CHANNEL DEVICES

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(X0) 15971225: FORMING A FIN USING DOUBLE TRENCH EPITAXY

(A1) 20180254333: FORMING A FIN USING DOUBLE TRENCH EPITAXY

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(X0) 15098722: SILICON GERMANIUM FINS ON INSULATOR FORMED BY LATERAL RECRYSTALLIZATION

(A1) 20170301697: SILICON GERMANIUM FINS ON INSULATOR FORMED BY LATERAL RECRYSTALLIZATION

(B2) 1: SILICON GERMANIUM FINS ON INSULATOR FORMED BY LATERAL RECRYSTALLIZATION

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(X0) 15954300: Low Resistance Source Drain Contact Formation

(A1) 20180240875: Low Resistance Source Drain Contact Formation

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(A1) 20160190304: A SEMICONDUCTOR INTEGRATED STRUCTURE HAVING AN EPITAXIAL SiGe LAYER EXTENDING FROM SILICON-CONTAINING REGIONS FORMED BETWEEN SEGMENTS OF OXIDE REGIONS

(B2) 1: A SEMICONDUCTOR INTEGRATED STRUCTURE HAVING AN EPITAXIAL SiGe LAYER EXTENDING FROM SILICON-CONTAINING REGIONS FORMED BETWEEN SEGMENTS OF OXIDE REGIONS

(X0) 14588221: A SEMICONDUCTOR INTEGRATED STRUCTURE HAVING AN EPITAXIAL SiGe LAYER EXTENDING FROM SILICON-CONTAINING REGIONS FORMED BETWEEN SEGMENTS OF OXIDE REGIONS

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(X0) 15884045: SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION

(A1) 20180175197: SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION

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(X0) 15270808: VOIDLESS CONTACT METAL STRUCTURES

(A1) 20170170064: VOIDLESS CONTACT METAL STRUCTURES

(B2) 9: VOIDLESS CONTACT METAL STRUCTURES

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(X0) 15808178: VERTICAL FIELD EFFECT TRANSISTOR WITH ABRUPT EXTENSIONS AT A BOTTOM SOURCE/DRAIN STRUCTURE

(B1) 9: VERTICAL FIELD EFFECT TRANSISTOR WITH ABRUPT EXTENSIONS AT A BOTTOM SOURCE/DRAIN STRUCTURE

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(X0) 15435974: FIN FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD TO FORM DEFECT FREE MERGED SOURCE AND DRAIN EPITAXY FOR LOW EXTERNAL RESISTANCE

(A1) 20170162671: FIN FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD TO FORM DEFECT FREE MERGED SOURCE AND DRAIN EPITAXY FOR LOW EXTERNAL RESISTANCE

(B2) 9: FIN FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD TO FORM DEFECT FREE MERGED SOURCE AND DRAIN EPITAXY FOR LOW EXTERNAL RESISTANCE

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(X0) 15859557: GATE TOP SPACER FOR FINFET

(A1) 20180145092: GATE TOP SPACER FOR FINFET

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(X0) 15849916: FORMING A FIN USING DOUBLE TRENCH EPITAXY

(A1) 20180138296: FORMING A FIN USING DOUBLE TRENCH EPITAXY

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(X0) 15674697: VTFET DEVICES UTILIZING LOW TEMPERATURE SELECTIVE EPITAXY

(A1) 20180122937: VTFET DEVICES UTILIZING LOW TEMPERATURE SELECTIVE EPITAXY

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(X0) 15596634: BOTTOM CONTACT RESISTANCE REDUCTION ON VFET

(B1) 9: BOTTOM CONTACT RESISTANCE REDUCTION ON VFET

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(X0) 15334058: MIS CAPACITOR FOR FINNED SEMICONDUCTOR STRUCTURE

(A1) 20180114869: MIS CAPACITOR FOR FINNED SEMICONDUCTOR STRUCTURE