SEARCH RESULTS for assignor:"LIU, RU-GUN"

Showing 1 to 20 of 38 results

Share this

Reel/Frame

Last Update:

Patent(s)

(X0) 15997513: Source Beam Optimization Method for Improving Lithography Printability

(A1) 20180285512: Source Beam Optimization Method for Improving Lithography Printability

Reel/Frame

Last Update:

Patent(s)

(X0) 15996099: Lithographic Technique Incorporating Varied Pattern Materials

(A1) 20180286698: Lithographic Technique Incorporating Varied Pattern Materials

Reel/Frame

Last Update:

Patent(s)

(X0) 15990147: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

(A1) 20180277358: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

Reel/Frame

Last Update:

Patent(s)

(X0) 15379084: Target Optimization Method For Improving Lithography Printability

(A1) 20180165397: Target Optimization Method For Improving Lithography Printability

(B2) 1: Target Optimization Method For Improving Lithography Printability

Reel/Frame

Last Update:

Patent(s)

(X0) 15179754: Multiple Patterning Method for Semiconductor Devices

(A1) 20170193147: Multiple Patterning Method for Semiconductor Devices

(B2) 1: Multiple Patterning Method for Semiconductor Devices

Reel/Frame

Last Update:

Patent(s)

(X0) 15362002: METHOD OF MANUFACTURING FINS AND SEMICONDUCTOR DEVICE WHICH INCLUDES FINS

(A1) 20170317089: METHOD OF MANUFACTURING FINS AND SEMICONDUCTOR DEVICE WHICH INCLUDES FINS

(B2) 1: METHOD OF MANUFACTURING FINS AND SEMICONDUCTOR DEVICE WHICH INCLUDES FINS

Reel/Frame

Last Update:

Patent(s)

(X0) 15436147: SEMICONDUCTOR DEVICE INCLUDING A TARGET INTEGRATED CIRCUIT PATTERN

(A1) 20170162435: SEMICONDUCTOR DEVICE INCLUDING A TARGET INTEGRATED CIRCUIT PATTERN

(B2) 1: SEMICONDUCTOR DEVICE INCLUDING A TARGET INTEGRATED CIRCUIT PATTERN

Reel/Frame

Last Update:

Patent(s)

(X0) 15170026: METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION

(A1) 20160275232: METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION

(B2) 1: METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION

Reel/Frame

Last Update:

Patent(s)

(X0) 15012205: Method for Patterning a Plurality of Features For Fin-Like Field-Effect Transistor (FINFET) Devices

(A1) 20160148815: Method for Patterning a Plurality of Features For Fin-Like Field-Effect Transistor (FINFET) Devices

(B2) 1: Method for Patterning a Plurality of Features For Fin-Like Field-Effect Transistor (FINFET) Devices

Reel/Frame

Last Update:

Patent(s)

(X0) 15395310: Directional Patterning Methods

(A1) 20180090370: Directional Patterning Methods

(B2) 1: Directional Patterning Methods

Reel/Frame

Last Update:

Patent(s)

(X0) 15602485: ENVIRONMENTAL-SURROUNDING-AWARE OPC

(A1) 20170262571: ENVIRONMENTAL-SURROUNDING-AWARE OPC

(B2) 1: ENVIRONMENTAL-SURROUNDING-AWARE OPC

Reel/Frame

Last Update:

Patent(s)

(X0) 15912177: Via Connection to a Partially Filled Trench

(A1) 20180197750: Via Connection to a Partially Filled Trench

Reel/Frame

Last Update:

Patent(s)

(X0) 15898882: POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

(A1) 20180174967: POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Reel/Frame

Last Update:

Patent(s)

(X0) 15382035: Fin-Like Field Effect Transistor Patterning Methods for Increasing Process Margins

(A1) 20180174854: Fin-Like Field Effect Transistor Patterning Methods for Increasing Process Margins

Reel/Frame

Last Update:

Patent(s)

(X0) 15474522: Pattern Fidelity Enhancement with Directional Patterning Technology

(A1) 20180174853: Pattern Fidelity Enhancement with Directional Patterning Technology

Reel/Frame

Last Update:

Patent(s)

(X0) 15474522: Pattern Fidelity Enhancement with Directional Patterning Technology

(A1) 20180174853: Pattern Fidelity Enhancement with Directional Patterning Technology

Reel/Frame

Last Update:

Patent(s)

(X0) 15427496: Method for Optimized Wafer Process Simulation

(A1) 20180165388: Method for Optimized Wafer Process Simulation

Reel/Frame

Last Update:

Patent(s)

(X0) 15689244: MULTIPLE PATTERNING DECOMPOSITION AND MANUFACTURING METHODS FOR IC

(A1) 20180164695: MULTIPLE PATTERNING DECOMPOSITION AND MANUFACTURING METHODS FOR IC

Reel/Frame

Last Update:

Patent(s)

(X0) 15249805: METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE

(A1) 20160365276: METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE

(B2) 9: METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE

Reel/Frame

Last Update:

Patent(s)

(X0) 15282131: Source Beam Optimization Method for Improving Lithography Printability

(A1) 20180096094: Source Beam Optimization Method for Improving Lithography Printability

(B2) 9: Source Beam Optimization Method for Improving Lithography Printability