SEARCH RESULTS for assignor:"HSIEH, KEN-HSIEN"

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(X0) 15990147: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

(A1) 20180277358: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

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(X0) 15379084: Target Optimization Method For Improving Lithography Printability

(A1) 20180165397: Target Optimization Method For Improving Lithography Printability

(B2) 1: Target Optimization Method For Improving Lithography Printability

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(X0) 15179754: Multiple Patterning Method for Semiconductor Devices

(A1) 20170193147: Multiple Patterning Method for Semiconductor Devices

(B2) 1: Multiple Patterning Method for Semiconductor Devices

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(X0) 15382035: Fin-Like Field Effect Transistor Patterning Methods for Increasing Process Margins

(A1) 20180174854: Fin-Like Field Effect Transistor Patterning Methods for Increasing Process Margins

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(X0) 15689244: MULTIPLE PATTERNING DECOMPOSITION AND MANUFACTURING METHODS FOR IC

(A1) 20180164695: MULTIPLE PATTERNING DECOMPOSITION AND MANUFACTURING METHODS FOR IC

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(X0) 15477588: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

(A1) 20170207081: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

(B2) 9: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

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(X0) 15477588: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

(A1) 20170207081: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

(B2) 9: LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK

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(X0) 15852129: Methods for Integrated Circuit Design and Fabrication

(A1) 20180138042: Methods for Integrated Circuit Design and Fabrication