SEARCH RESULTS for assignor:"CHANG, YAO-WEN"

Showing 1 to 8 of 8 results

Last Update Patent(s) Assignor(s) Orig. Assignee(s) Assignee(s) Reel/Frame
31-May-2018

(X0) 1: Film Scheme for Bumping

(A1) 2: Film Scheme for Bumping

CHANG, YAO-WEN

HSU, CHERN-YOW

TSAI, CHENG-YUAN

THEI, KONG-BENG

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

44025/696

24-May-2018

(X0) 1: METHOD FOR LEGALIZING MIXED-CELL HEIGHT STANDARD CELLS OF IC

(A1) 2: METHOD FOR LEGALIZING MIXED-CELL HEIGHT STANDARD CELLS OF IC

WANG, CHAO-HUNG

WU, YEN-YI

CHEN, SHIH-CHUN

CHANG, YAO-WEN

HSU, MENG-KAI

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

40533/658

22-May-2018

(X0) 1: METHOD FOR OPERATING MEMORY ARRAY

(B1) 9: METHOD FOR OPERATING MEMORY ARRAY

(A1) 2: METHOD FOR OPERATING MEMORY ARRAY

(B2) 9: METHOD FOR OPERATING MEMORY ARRAY

CHEN, YUNG-HSIANG

CHANG, YAO-WEN

YANG, I-CHEN

MACRONIX INTERNATIONAL CO., LTD.

40399/87

17-May-2018

(X0) 1: METHOD FOR OPERATING MEMORY ARRAY

(A1) 2: METHOD FOR OPERATING MEMORY ARRAY

WU, GUAN-WEI

CHANG, YAO-WEN

YANG, I-CHEN

MACRONIX INTERNATIONAL CO., LTD.

40302/540

10-Apr-2018

(X0) 1: SYSTEMS AND METHODS FOR MINIMUM-IMPLANT-AREA AWARE DETAILED PLACEMENT

(A1) 2: SYSTEMS AND METHODS FOR MINIMUM-IMPLANT-AREA AWARE DETAILED PLACEMENT

(B2) 9: SYSTEMS AND METHODS FOR MINIMUM-IMPLANT-AREA AWARE DETAILED PLACEMENT

CHANG, YAO-WEN

TSENG, KAI-HAN

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

39498/751

06-Feb-2018

(X0) 1: SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURE THEREOF, AND METHODS OF SINGULATING SEMICONDUCTOR DEVICES

(A1) 2: SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURE THEREOF, AND METHODS OF SINGULATING SEMICONDUCTOR DEVICES

(B2) 9: SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURE THEREOF, AND METHODS OF SINGULATING SEMICONDUCTOR DEVICES

CHANG, YAO-WEN

HUANG, JIAN-SHIOU

TSAI, CHENG-YUAN

THEI, KONG-BENG

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

38764/931

01-Feb-2018

(B2) 9: Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages

(X0) 1: Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages

(A1) 2: Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages

LIN, BO-QIAO

LIN, TING-CHOU

YANG, CHUN-YI

CHANG, YAO-WEN

ANAGLOBE TECHNOLOGY, INC.

39373/916

02-Jan-2018

(X0) 1: METHOD FOR OPERATING A MEMORY DEVICE

(B1) 9: METHOD FOR OPERATING A MEMORY DEVICE

LIN, TAO-YUAN

YANG, I-CHEN

CHANG, YAO-WEN

MACRONIX INTERNATIONAL CO., LTD.

40744/264