SEARCH RESULTS for assignee:"GLOBALFOUNDRIES INC."

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(X0) 15995896: DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS

(A1) 20180286873: DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS

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(X0) 15996960: SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL INCLUDING LONG VIA LINES

(A1) 20180286773: SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL INCLUDING LONG VIA LINES

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(X0) 15997368: PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH

(A1) 20180286967: PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH

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(X0) 16002070: INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

(A1) 20180286863: INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

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(X0) 15478441: METHODS OF IDENTIFYING SPACE WITHIN INTEGRATED CIRCUIT STRUCTURE AS MANDREL SPACE OR NON-MANDREL SPACE

(A1) 20180286681: METHODS OF IDENTIFYING SPACE WITHIN INTEGRATED CIRCUIT STRUCTURE AS MANDREL SPACE OR NON-MANDREL SPACE

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(X0) 15478666: ZERO TEST TIME MEMORY USING BACKGROUND BUILT-IN SELF-TEST

(A1) 20180286491: ZERO TEST TIME MEMORY USING BACKGROUND BUILT-IN SELF-TEST

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(X0) 15478377: SRAF INSERTION WITH ARTIFICIAL NEURAL NETWORK

(A1) 20180285510: SRAF INSERTION WITH ARTIFICIAL NEURAL NETWORK

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(X0) 15474104: APPARATUS FOR AND METHOD OF NET TRACE PRIOR LEVEL SUBTRACTION

(A1) 20180284184: APPARATUS FOR AND METHOD OF NET TRACE PRIOR LEVEL SUBTRACTION

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(X0) 15474354: TRANSISTOR STRUCTURES

(A1) 20180286801: TRANSISTOR STRUCTURES

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(X0) 15475873: FINFETs WITH STRAINED CHANNELS AND REDUCED ON STATE RESISTANCE

(A1) 20180286982: FINFETs WITH STRAINED CHANNELS AND REDUCED ON STATE RESISTANCE

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(X0) 15477565: METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

(A1) 20180286956: METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

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(X0) 15473043: SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS WITH A BASE GROWN IN A DIELECTRIC CAVITY

(A1) 20180286968: SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS WITH A BASE GROWN IN A DIELECTRIC CAVITY

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(X0) 15475475: ETCH KERNEL DEFINITION FOR ETCH MODELING

(A1) 20180284597: ETCH KERNEL DEFINITION FOR ETCH MODELING

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(X0) 15010868: DICING CHANNELS FOR GLASS INTERPOSERS

(A1) 20170221837: DICING CHANNELS FOR GLASS INTERPOSERS

(B2) 1: DICING CHANNELS FOR GLASS INTERPOSERS

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(X0) 15172551: INTERCONNECT STRUCTURE WITH CAPACITOR ELEMENT AND RELATED METHODS

(A1) 20170352619: INTERCONNECT STRUCTURE WITH CAPACITOR ELEMENT AND RELATED METHODS

(B2) 1: INTERCONNECT STRUCTURE WITH CAPACITOR ELEMENT AND RELATED METHODS

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(X0) 15257245: METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCTOR STRUCTURE INCLUDING A DIFFUSION BARRIER

(A1) 20170117179: METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCTOR STRUCTURE INCLUDING A DIFFUSION BARRIER

(B2) 1: METHOD INCLUDING A FORMATION OF A DIFFUSION BARRIER AND SEMICONDUCTOR STRUCTURE INCLUDING A DIFFUSION BARRIER

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(X0) 15357287: SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

(A1) 20170125299: SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

(B2) 1: SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

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(A1) 20180286965: METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING OPENING FILLED WITH INSULATOR IN METAL GATE

(B2) 1: METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING OPENING FILLED WITH INSULATOR IN METAL GATE

(X0) 15475272: METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING OPENING FILLED WITH INSULATOR IN METAL GATE

(B1) 1: METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING OPENING FILLED WITH INSULATOR IN METAL GATE

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(A1) 20180286951: METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE WITH A CHANNEL STRUCTURE COMPRISED OF ALTERNATIVE SEMICONDUCTOR MATERIALS

(B2) 1: METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE WITH A CHANNEL STRUCTURE COMPRISED OF ALTERNATIVE SEMICONDUCTOR MATERIALS

(X0) 15475946: METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE WITH A CHANNEL STRUCTURE COMPRISED OF ALTERNATIVE SEMICONDUCTOR MATERIALS

(B1) 1: METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE WITH A CHANNEL STRUCTURE COMPRISED OF ALTERNATIVE SEMICONDUCTOR MATERIALS

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