SEARCH RESULTS for assignee:"GLOBALFOUNDRIES INC."

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(X0) 13943849: SEMICONDUCTOR DEVICE HAVING LOCAL BURIED OXIDE

(A1) 20150024557: SEMICONDUCTOR DEVICE HAVING LOCAL BURIED OXIDE

(B2) 1: SEMICONDUCTOR DEVICE HAVING LOCAL BURIED OXIDE

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(X0) 14812046: METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE

(A1) 20160163559: METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE

(B2) 1: METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE

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(X0) 15055571: STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

(A1) 20170162582: STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

(B2) 1: STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

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(X0) 15178871: SELF-ALIGNED FINFET FORMATION

(A1) 20170358662: SELF-ALIGNED FINFET FORMATION

(B2) 1: SELF-ALIGNED FINFET FORMATION

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(X0) 15227142: FORMING A CONTACT FOR A TALL FIN TRANSISTOR

(A1) 20170047226: FORMING A CONTACT FOR A TALL FIN TRANSISTOR

(B2) 1: FORMING A CONTACT FOR A TALL FIN TRANSISTOR

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(X0) 15244067: FORMING A GATE CONTACT IN THE ACTIVE AREA

(A1) 20170054004: FORMING A GATE CONTACT IN THE ACTIVE AREA

(B2) 1: FORMING A GATE CONTACT IN THE ACTIVE AREA

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(X0) 15268796: METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE

(A1) 20180083136: METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE

(B2) 1: METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE

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(X0) 15375623: PHOTOMASK BLANK INCLUDING A THIN CHROMIUM HARDMASK

(A1) 20180164674: PHOTOMASK BLANK INCLUDING A THIN CHROMIUM HARDMASK

(B2) 1: PHOTOMASK BLANK INCLUDING A THIN CHROMIUM HARDMASK

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(X0) 15422689: DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY

(B1) 1: DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY

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(X0) 15424379: VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

(A1) 20180226505: VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

(B2) 1: VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

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(X0) 15437840: SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS

(A1) 20180240889: SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS

(B2) 1: SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS

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(X0) 15626241: SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR

(A1) 20170288033: SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR

(B2) 1: SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR

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(X0) 15634091: DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS

(A1) 20170294336: DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS

(B2) 1: DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS

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(X0) 15709704: MEMORY CELL WITH RECESSED SOURCE/DRAIN CONTACTS TO REDUCE CAPACITANCE

(B1) 1: MEMORY CELL WITH RECESSED SOURCE/DRAIN CONTACTS TO REDUCE CAPACITANCE

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(X0) 15719861: CHAMFERING FOR STRESS REDUCTION ON PASSIVATION LAYER

(B1) 1: CHAMFERING FOR STRESS REDUCTION ON PASSIVATION LAYER

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(X0) 15787009: INTEGRATED CIRCUIT STRUCTURE INCORPORATING MULTIPLE GATE-ALL-AROUND FIELD EFFECT TRANSISTORS HAVING DIFFERENT DRIVE CURRENTS AND METHOD

(B1) 1: INTEGRATED CIRCUIT STRUCTURE INCORPORATING MULTIPLE GATE-ALL-AROUND FIELD EFFECT TRANSISTORS HAVING DIFFERENT DRIVE CURRENTS AND METHOD

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(X0) 15792206: HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

(A1) 20180047824: HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

(B2) 1: HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

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(X0) 15793621: SELF-ALIGNED NANOTUBE STRUCTURES

(B1) 1: SELF-ALIGNED NANOTUBE STRUCTURES

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(X0) 15811745: FORMING LONG CHANNEL FinFET WITH SHORT CHANNEL VERTICAL FinFET AND RELATED INTEGRATED CIRCUIT

(B1) 1: FORMING LONG CHANNEL FinFET WITH SHORT CHANNEL VERTICAL FinFET AND RELATED INTEGRATED CIRCUIT

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