SEARCH RESULTS for assignor:"JAGANNATHAN, HEMANTH"

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(X0) 15416281: APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES

(A1) 20180212037: APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES

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(X0) 15918199: APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES

(A1) 20180212040: APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES

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(X0) 15412499: FORMATION OF COMMON INTERFACIAL LAYER ON Si/SiGe DUAL CHANNEL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE

(A1) 20180211885: FORMATION OF COMMON INTERFACIAL LAYER ON Si/SiGe DUAL CHANNEL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE

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(X0) 15603982: SIMPLIFIED GATE STACK PROCESS TO IMPROVE DUAL CHANNEL CMOS PERFORMANCE

(A1) 20180089479: SIMPLIFIED GATE STACK PROCESS TO IMPROVE DUAL CHANNEL CMOS PERFORMANCE

(B2) 9: SIMPLIFIED GATE STACK PROCESS TO IMPROVE DUAL CHANNEL CMOS PERFORMANCE

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(X0) 15859340: HIGH-K LAYER CHAMFERING TO PREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS

(A1) 20180145150: HIGH-K LAYER CHAMFERING TO PREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS

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(X0) 14964445: METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS

(A1) 20170170171: METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS

(B2) 9: METHOD OF CUTTING FINS TO CREATE DIFFUSION BREAKS FOR FINFETS

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(X0) 15855078: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

(A1) 20180138093: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

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(X0) 15855049: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

(A1) 20180122646: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

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(X0) 15596634: BOTTOM CONTACT RESISTANCE REDUCTION ON VFET

(B1) 9: BOTTOM CONTACT RESISTANCE REDUCTION ON VFET

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(X0) 15224876: SELECTIVE THICKENING OF PFET DIELECTRIC

(A1) 20160343622: SELECTIVE THICKENING OF PFET DIELECTRIC

(B2) 9: SELECTIVE THICKENING OF PFET DIELECTRIC

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(X0) 15722193: CONTROLLING THRESHOLD VOLTAGE IN NANOSHEET TRANSISTORS

(A1) 20180090326: CONTROLLING THRESHOLD VOLTAGE IN NANOSHEET TRANSISTORS

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(X0) 15825688: MASKLESS METHOD TO REDUCE SOURCE-DRAIN CONTACT RESISTANCE IN CMOS DEVICES

(A1) 20180083114: MASKLESS METHOD TO REDUCE SOURCE-DRAIN CONTACT RESISTANCE IN CMOS DEVICES

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(X0) 15262206: FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE

(A1) 20180076040: FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE

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(X0) 15259626: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

(A1) 20180068857: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

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(X0) 15334479: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

(A1) 20180068903: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

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(X0) 15334568: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

(A1) 20180068904: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

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(X0) 15259626: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

(A1) 20180068857: LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

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(X0) 15254302: MASKLESS METHOD TO REDUCE SOURCE-DRAIN CONTACT RESISTANCE IN CMOS DEVICES

(A1) 20180061956: MASKLESS METHOD TO REDUCE SOURCE-DRAIN CONTACT RESISTANCE IN CMOS DEVICES

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(X0) 14149088: REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS

(A1) 20140117466: REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS

(B2) 9: REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS

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(X0) 15613930: FABRICATION OF SILICON-GERMANIUM FIN STRUCTURE HAVING SILICON-RICH OUTER SURFACE

(A1) 20180026100: FABRICATION OF SILICON-GERMANIUM FIN STRUCTURE HAVING SILICON-RICH OUTER SURFACE