SEARCH RESULTS for assignee:"TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD." AND day:[2019-01-01T00:00:00Z TO 2019-01-01T23:59:59Z]

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(X0) 15154986: HIGH RESISTANCE VIRTUAL ANODE FOR ELECTROPLATING CELL

(A1) 20170152607: HIGH RESISTANCE VIRTUAL ANODE FOR ELECTROPLATING CELL

(B2) 1: HIGH RESISTANCE VIRTUAL ANODE FOR ELECTROPLATING CELL

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(X0) 15221187: CHEMICAL-MECHANICAL PLANARIZATION SYSTEM

(A1) 20160332277: CHEMICAL-MECHANICAL PLANARIZATION SYSTEM

(B2) 1: CHEMICAL-MECHANICAL PLANARIZATION SYSTEM

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(X0) 15242697: DYNAMIC ESD PROTECTION SCHEME

(A1) 20170346278: DYNAMIC ESD PROTECTION SCHEME

(B2) 1: DYNAMIC ESD PROTECTION SCHEME

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(X0) 15271272: ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

(A1) 20170141100: ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

(B2) 1: ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

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(X0) 15354808: PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

(A1) 20180138911: PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

(B2) 1: PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

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(X0) 15404937: FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

(A1) 20170125307: FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

(B2) 1: FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

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(X0) 15431802: METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

(A1) 20180151537: METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

(B2) 1: METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

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(X0) 15433353: RRAM CELL BOTTOM ELECTRODE FORMATION

(A1) 20170162787: RRAM CELL BOTTOM ELECTRODE FORMATION

(B2) 1: RRAM CELL BOTTOM ELECTRODE FORMATION

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(X0) 15439794: VARIATION-AWARE CIRCUIT SIMULATION

(A1) 20180150577: VARIATION-AWARE CIRCUIT SIMULATION

(B2) 1: VARIATION-AWARE CIRCUIT SIMULATION

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(X0) 15453963: SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE AND FABRICATION METHOD OF THE SAME

(A1) 20180151494: SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE AND FABRICATION METHOD OF THE SAME

(B2) 1: SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE AND FABRICATION METHOD OF THE SAME

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(X0) 15489019: METHOD FOR FORMING IMAGE SENSOR DEVICE

(A1) 20180301502: METHOD FOR FORMING IMAGE SENSOR DEVICE

(B2) 1: METHOD FOR FORMING IMAGE SENSOR DEVICE

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(X0) 15496491: NOVEL PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE

(A1) 20170229397: NOVEL PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE

(B2) 1: NOVEL PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE

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(X0) 15498748: GATE ALL-AROUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

(A1) 20180151452: GATE ALL-AROUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

(B2) 1: GATE ALL-AROUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

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(X0) 15489875: REDUCTION OF DISHING DURING CHEMICAL MECHANICAL POLISH OF GATE STRUCTURE

(A1) 20180301348: REDUCTION OF DISHING DURING CHEMICAL MECHANICAL POLISH OF GATE STRUCTURE

(B2) 1: REDUCTION OF DISHING DURING CHEMICAL MECHANICAL POLISH OF GATE STRUCTURE

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(X0) 15487573: IMPLANTATION PROCESS FOR SEMICONDUCTOR DEVICE

(A1) 20180301496: IMPLANTATION PROCESS FOR SEMICONDUCTOR DEVICE

(B2) 1: IMPLANTATION PROCESS FOR SEMICONDUCTOR DEVICE

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(X0) 15616138: SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

(A1) 20170271198: SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

(B2) 1: SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

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(X0) 15632449: SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

(A1) 20180277448: SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

(B2) 1: SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

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(X0) 15638463: POST-CMP CLEANING APPARATUS AND METHOD WITH BRUSH SELF-CLEANING FUNCTION

(B1) 1: POST-CMP CLEANING APPARATUS AND METHOD WITH BRUSH SELF-CLEANING FUNCTION

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(X0) 15697150: STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH BIPOLAR JUNCTION TRANSISTOR

(A1) 20180166564: STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH BIPOLAR JUNCTION TRANSISTOR

(B2) 1: STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH BIPOLAR JUNCTION TRANSISTOR