Share this

Patent Assignment 20640/889

ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

  • Date Recorded: Mar 12, 2008
  • Assignor(s)

  • Assignee

    ANAPASS INC.

    3F. KFSB B/D., 16-2, YEOUIDO-DONG, YEONGDEUNGPO-GU
    SEOUL
    1
    KOREA, REPUBLIC OF
  • Reel/Frame: 20640/{889}
  • Correspondent

    DANIEL H. SHERR

    620 HERNDON PARKWAY
    SUITE 200
    HERNDON, VA 20170

Properties

Patent Publication Application
Display, Timing Controller and Column Driver Integrated Circuit Using Clock Embedded Multi-Level Signaling (A1) 20080246752
Oct 09, 2008
(B2) 9934712
Apr 03, 2018
(X0) 12066553
Mar 12, 2008