SEARCH RESULTS for assignee:"taiwan semiconductor manufacturing company ltd"

Showing 1 to 20 of 129 results

Share this

Reel/Frame

Last Update:

Patent(s)

(X0) 15902431: CIRCUIT, SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION

(A1) 20190115339: CIRCUIT, SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Reel/Frame

Last Update:

Patent(s)

(X0) 15937230: METHOD FOR ROLE-BASED DATA TRANSMISSION USING PHYSICALLY UNCLONABLE FUNCTION (PUF)-BASED KEYS

(A1) 20190116028: METHOD FOR ROLE-BASED DATA TRANSMISSION USING PHYSICALLY UNCLONABLE FUNCTION (PUF)-BASED KEYS

Reel/Frame

Last Update:

Patent(s)

(X0) 16206803: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

(A1) 20190115261: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

Reel/Frame

Last Update:

Patent(s)

(X0) 16206730: METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

(A1) 20190115438: METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Reel/Frame

Last Update:

Patent(s)

(X0) 16206771: METHOD FOR TESTING BRIDGING IN ADJACENT SEMICONDUCTOR DEVICES AND TEST STRUCTURE

(A1) 20190115266: METHOD FOR TESTING BRIDGING IN ADJACENT SEMICONDUCTOR DEVICES AND TEST STRUCTURE

Reel/Frame

Last Update:

Patent(s)

(X0) 16206881: STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD

(A1) 20190114382: STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD

Reel/Frame

Last Update:

Patent(s)

(X0) 16207056: OVERLAY MARK

(A1) 20190115303: OVERLAY MARK

Reel/Frame

Last Update:

Patent(s)

(X0) 16214177: Method and Structure for Semiconductor Mid-End-Of-Year (MEOL) Process

(A1) 20190115336: Method and Structure for Semiconductor Mid-End-Of-Year (MEOL) Process

Reel/Frame

Last Update:

Patent(s)

(X0) 16214187: Surface Treatment and Passivation for High Electron Mobility Transistors

(A1) 20190115447: Surface Treatment and Passivation for High Electron Mobility Transistors

Reel/Frame

Last Update:

Patent(s)

(X0) 16214403: FinFET Transistor with Fin Back Biasing

(A1) 20190115345: FinFET Transistor with Fin Back Biasing

Reel/Frame

Last Update:

Patent(s)

(X0) 16217095: Immersion Lithography System Using a Sealed Wafer Bath

(A1) 20190113855: Immersion Lithography System Using a Sealed Wafer Bath

Reel/Frame

Last Update:

Patent(s)

(X0) 16218578: Structure and Method for MOSFET Device

(A1) 20190115349: Structure and Method for MOSFET Device

Reel/Frame

Last Update:

Patent(s)

(X0) 16218591: Integrated Circuit with Conductive Line Having Line-Ends

(A1) 20190115250: Integrated Circuit with Conductive Line Having Line-Ends

Reel/Frame

Last Update:

Patent(s)

(X0) 16218614: Systems and Methods for in SITU Maintenance of a Thin Hardmask During an Etch Process

(A1) 20190115225: Systems and Methods for in SITU Maintenance of a Thin Hardmask During an Etch Process

Reel/Frame

Last Update:

Patent(s)

(X0) 16218651: FINFET Device Having A Channel Defined In A Diamond-Like Shape Semiconductor Structure

(A1) 20190115453: FINFET Device Having A Channel Defined In A Diamond-Like Shape Semiconductor Structure

Reel/Frame

Last Update:

Patent(s)

(X0) 16219114: Mask with Multilayer Structure and Manufacturing Method by Using the Same

(A1) 20190113835: Mask with Multilayer Structure and Manufacturing Method by Using the Same

Reel/Frame

Last Update:

Patent(s)

(X0) 16229260: Method of Forming Source/Drain Contact

(A1) 20190115262: Method of Forming Source/Drain Contact

Reel/Frame

Last Update:

Patent(s)

(X0) 16230534: Method of Forming Metal Interconnection

(A1) 20190115297: Method of Forming Metal Interconnection

Reel/Frame

Last Update:

Patent(s)

(X0) 16129433: SYSTEMS AND METHODS FOR DETERMINING SYSTEMATIC DEFECTS

(A1) 20190113573: SYSTEMS AND METHODS FOR DETERMINING SYSTEMATIC DEFECTS

Reel/Frame

Last Update:

Patent(s)

(X0) 16206803: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

(A1) 20190115261: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME