SEARCH RESULTS for assignee:"taiwan semiconductor manufacturing"

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(X0) 15586599: PHOTOMASK AND FABRICATION METHOD THEREFOR

(A1) 20180321581: PHOTOMASK AND FABRICATION METHOD THEREFOR

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(X0) 15588804: SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

(A1) 20180323259: SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

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(X0) 15588830: SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

(A1) 20180323312: SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

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(X0) 16022680: SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM

(A1) 20180323182: SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM

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(X0) 16024291: SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

(A1) 20180323303: SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

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(X0) 16033401: Method for Forming Stacked Nanowire Transistors

(A1) 20180323065: Method for Forming Stacked Nanowire Transistors

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(X0) 15589659: METHOD FOR FORMING A LOW-K SPACER

(A1) 20180323276: METHOD FOR FORMING A LOW-K SPACER

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(X0) 16022687: OUTPUT RESISTANCE TESTING METHOD

(A1) 20180321291: OUTPUT RESISTANCE TESTING METHOD

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(X0) 16025786: STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR

(A1) 20180323112: STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR

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(X0) 15471937: DUAL RAIL DEVICE WITH POWER DETECTOR FOR CONTROLLING POWER TO FIRST AND SECOND POWER DOMAINS

(A1) 20180174643: DUAL RAIL DEVICE WITH POWER DETECTOR FOR CONTROLLING POWER TO FIRST AND SECOND POWER DOMAINS

(B2) 1: DUAL RAIL DEVICE WITH POWER DETECTOR FOR CONTROLLING POWER TO FIRST AND SECOND POWER DOMAINS

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(X0) 14927822: Elongated Semiconductor Structure Planarization

(A1) 20170125518: Elongated Semiconductor Structure Planarization

(B2) 1: Elongated Semiconductor Structure Planarization

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(X0) 15250934: INTEGRATED FAN-OUT PACKAGE AND LAYOUT METHOD THEREOF

(A1) 20180060479: INTEGRATED FAN-OUT PACKAGE AND LAYOUT METHOD THEREOF

(B2) 1: INTEGRATED FAN-OUT PACKAGE AND LAYOUT METHOD THEREOF

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(X0) 15365064: STACKED SUBSTRATE STRUCTURE WITH INTER-TIER INTERCONNECTION

(A1) 20170186799: STACKED SUBSTRATE STRUCTURE WITH INTER-TIER INTERCONNECTION

(B2) 1: STACKED SUBSTRATE STRUCTURE WITH INTER-TIER INTERCONNECTION

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(X0) 13798581: MULTI-PLATEN ION IMPLANTER AND METHOD FOR IMPLANTING MULTIPLE SUBSTRATES SIMULTANEOUSLY

(A1) 20140272178: MULTI-PLATEN ION IMPLANTER AND METHOD FOR IMPLANTING MULTIPLE SUBSTRATES SIMULTANEOUSLY

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(X0) 14861441: BOTTOM-UP PEALD PROCESS

(A1) 20160013043: BOTTOM-UP PEALD PROCESS

(B2) 1: BOTTOM-UP PEALD PROCESS

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(B2) 1: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

(X0) 15649909: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

(A1) 20180190504: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

(B2) 1: SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

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(X0) 15692169: SEMICONDUCTOR DEVICE STRUCTURE WITH STRAIN-RELAXED BUFFER

(B1) 1: SEMICONDUCTOR DEVICE STRUCTURE WITH STRAIN-RELAXED BUFFER

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(X0) 15686916: METHOD OF HIGH-ASPECT RATIO PATTERN FORMATION WITH SUBMICRON PIXEL PITCH

(B1) 1: METHOD OF HIGH-ASPECT RATIO PATTERN FORMATION WITH SUBMICRON PIXEL PITCH

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(X0) 15960815: MEMORY ARRAY AND METHOD OF FORMING THE SAME

(A1) 20180240505: MEMORY ARRAY AND METHOD OF FORMING THE SAME

(B2) 1: MEMORY ARRAY AND METHOD OF FORMING THE SAME

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(X0) 15429894: Metal Gate and Contact Plug Design and Method Forming Same

(A1) 20180033866: Metal Gate and Contact Plug Design and Method Forming Same

(B2) 1: Metal Gate and Contact Plug Design and Method Forming Same