SEARCH RESULTS for assignee:"taiwan semiconductor manufacturing"

Showing 1 to 20 of 90 results

Share this

Reel/Frame

Last Update:

Patent(s)

(X0) 14259585: MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF

(A1) 20140232009: MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF

(B2) 1: MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF

Reel/Frame

Last Update:

Patent(s)

(X0) 14284699: Through Via Structure Extending to Metallization Layer

(A1) 20150235922: Through Via Structure Extending to Metallization Layer

(B2) 1: Through Via Structure Extending to Metallization Layer

Reel/Frame

Last Update:

Patent(s)

(X0) 14319610: FINFET THERMAL PROTECTION METHODS AND RELATED STRUCTURES

(A1) 20150380558: FINFET THERMAL PROTECTION METHODS AND RELATED STRUCTURES

(B2) 1: FINFET THERMAL PROTECTION METHODS AND RELATED STRUCTURES

Reel/Frame

Last Update:

Patent(s)

(X0) 14458850: Apparatus for High Speed ROM Cells

(A1) 20160049412: Apparatus for High Speed ROM Cells

(B2) 1: Apparatus for High Speed ROM Cells

Reel/Frame

Last Update:

Patent(s)

(X0) 14755795: Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

(A1) 20170005067: Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

(B2) 1: Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

Reel/Frame

Last Update:

Patent(s)

(X0) 14583444: SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

(A1) 20160190249: SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

(B2) 1: SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Reel/Frame

Last Update:

Patent(s)

(X0) 14942927: LAYOUT MODIFICATION METHOD AND SYSTEM

(A1) 20170140086: LAYOUT MODIFICATION METHOD AND SYSTEM

(B2) 1: LAYOUT MODIFICATION METHOD AND SYSTEM

Reel/Frame

Last Update:

Patent(s)

(X0) 15143824: SYSTEMS AND METHODS FOR A TUNABLE ELECTROMAGNETIC FIELD APPARATUS TO IMPROVE DOPING UNIFORMITY

(A1) 20170316942: SYSTEMS AND METHODS FOR A TUNABLE ELECTROMAGNETIC FIELD APPARATUS TO IMPROVE DOPING UNIFORMITY

(B2) 1: SYSTEMS AND METHODS FOR A TUNABLE ELECTROMAGNETIC FIELD APPARATUS TO IMPROVE DOPING UNIFORMITY

Reel/Frame

Last Update:

Patent(s)

(X0) 15154986: HIGH RESISTANCE VIRTUAL ANODE FOR ELECTROPLATING CELL

(A1) 20170152607: HIGH RESISTANCE VIRTUAL ANODE FOR ELECTROPLATING CELL

(B2) 1: HIGH RESISTANCE VIRTUAL ANODE FOR ELECTROPLATING CELL

Reel/Frame

Last Update:

Patent(s)

(X0) 15221187: CHEMICAL-MECHANICAL PLANARIZATION SYSTEM

(A1) 20160332277: CHEMICAL-MECHANICAL PLANARIZATION SYSTEM

(B2) 1: CHEMICAL-MECHANICAL PLANARIZATION SYSTEM

Reel/Frame

Last Update:

Patent(s)

(X0) 15242697: DYNAMIC ESD PROTECTION SCHEME

(A1) 20170346278: DYNAMIC ESD PROTECTION SCHEME

(B2) 1: DYNAMIC ESD PROTECTION SCHEME

Reel/Frame

Last Update:

Patent(s)

(X0) 15271272: ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

(A1) 20170141100: ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

(B2) 1: ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

Reel/Frame

Last Update:

Patent(s)

(X0) 15299711: CIRCUIT DESIGN METHOD AND SYSTEM

(A1) 20170039310: CIRCUIT DESIGN METHOD AND SYSTEM

(B2) 1: CIRCUIT DESIGN METHOD AND SYSTEM

Reel/Frame

Last Update:

Patent(s)

(X0) 15333439: DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME

(A1) 20170047333: DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME

(B2) 1: DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME

Reel/Frame

Last Update:

Patent(s)

(X0) 15339423: Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel

(A1) 20170047432: Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel

(B2) 1: Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel

Reel/Frame

Last Update:

Patent(s)

(X0) 15354808: PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

(A1) 20180138911: PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

(B2) 1: PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

Reel/Frame

Last Update:

Patent(s)

(X0) 15399180: APPARATUS AND A METHOD OF FORMING A PARTICLE SHIELD

(A1) 20170363974: APPARATUS AND A METHOD OF FORMING A PARTICLE SHIELD

(B2) 1: APPARATUS AND A METHOD OF FORMING A PARTICLE SHIELD

Reel/Frame

Last Update:

Patent(s)

(X0) 15404937: FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

(A1) 20170125307: FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

(B2) 1: FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

Reel/Frame

Last Update:

Patent(s)

(X0) 15413071: METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

(A1) 20170186584: METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

(B2) 1: METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

Reel/Frame

Last Update:

Patent(s)

(X0) 15431802: METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

(A1) 20180151537: METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

(B2) 1: METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND