SEARCH RESULTS for assignee:"synopsys"

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(X0) 14069326: VISUAL REPRESENTATION OF CIRCUIT RELATED DATA

(A1) 20150120250: VISUAL REPRESENTATION OF CIRCUIT RELATED DATA

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(B2) 10409941: VISUAL REPRESENTATION OF CIRCUIT RELATED DATA

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(X0) 16289841: MEMORY ARRAY ARCHITECTURES FOR MEMORY QUEUES

(A1) 20190272120: MEMORY ARRAY ARCHITECTURES FOR MEMORY QUEUES

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(X0) 14016010: DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS

(A1) 20150040090: DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS

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(B2) 10394993: DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS

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(X0) 16047976: Formal Clock Network Analysis, Visualization, Verification and Generation

(A1) 20190034571: Formal Clock Network Analysis, Visualization, Verification and Generation

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(X0) 12695391: MULTI-THREADED GLOBAL ROUTING

(A1) 20110055784: MULTI-THREADED GLOBAL ROUTING

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(B2) 10387604: MULTI-THREADED GLOBAL ROUTING

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(X0) 15713506: Virtual Terminals for Linear-Parameter Extraction

(A1) 20180089353: Virtual Terminals for Linear-Parameter Extraction

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(X0) 13886891: FORMAL VERIFICATION RESULT PREDICTION

(A1) 20140330758: FORMAL VERIFICATION RESULT PREDICTION

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(B2) 10366330: FORMAL VERIFICATION RESULT PREDICTION

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(X0) 14184548: COMPACT OPC MODEL GENERATION USING VIRTUAL DATA

(A1) 20140244226: COMPACT OPC MODEL GENERATION USING VIRTUAL DATA

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(B2) 10365557: COMPACT OPC MODEL GENERATION USING VIRTUAL DATA

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(X0) 14044561: AUGMENTED POWER-AWARE DECOMPRESSOR

(A1) 20140095101: AUGMENTED POWER-AWARE DECOMPRESSOR

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(B2) 10345369: AUGMENTED POWER-AWARE DECOMPRESSOR

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(X0) 14167716: INVARIANT SHARING TO SPEED UP FORMAL VERIFICATION

(A1) 20150213167: INVARIANT SHARING TO SPEED UP FORMAL VERIFICATION

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(B2) 10325054: INVARIANT SHARING TO SPEED UP FORMAL VERIFICATION

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(X0) 16207567: Phase-Aware Control and Scheduling

(A1) 20190171598: Phase-Aware Control and Scheduling

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(X0) 13561918: LAYOUT-AWARE TEST PATTERN GENERATION AND FAULT DETECTION

(A1) 20140032156: LAYOUT-AWARE TEST PATTERN GENERATION AND FAULT DETECTION

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(B2) 10254343: LAYOUT-AWARE TEST PATTERN GENERATION AND FAULT DETECTION

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(X0) 15905555: COMPACT MODELING FOR THE NEGATIVE TONE DEVELOPMENT PROCESSES

(A1) 20190072847: COMPACT MODELING FOR THE NEGATIVE TONE DEVELOPMENT PROCESSES

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(X0) 16136033: System and Method for Hierarchical Power Verification

(A1) 20190018913: System and Method for Hierarchical Power Verification

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(X0) 14519418: OPTICAL DESIGN USING FREEFORM TAILORING

(A1) 20150127304: OPTICAL DESIGN USING FREEFORM TAILORING

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(B2) 10151921: OPTICAL DESIGN USING FREEFORM TAILORING

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(X0) 15604560: Rule Based Assist Feature Placement Using Skeletons

(A1) 20180341740: Rule Based Assist Feature Placement Using Skeletons

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(X0) 15595425: Architecture, System and Method for Creating and Employing Trusted Virtual Appliances

(A1) 20180329736: Architecture, System and Method for Creating and Employing Trusted Virtual Appliances

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