SEARCH RESULTS for assignee:"nvidia"

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(X0) 15795091: SYMMETRIC BLOCK SPARSE MATRIX-VECTOR MULTIPLICATION

(A1) 20180121388: SYMMETRIC BLOCK SPARSE MATRIX-VECTOR MULTIPLICATION

(B2) 1: SYMMETRIC BLOCK SPARSE MATRIX-VECTOR MULTIPLICATION

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(X0) 14613339: APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

(A1) 20170192822: APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

(B2) 1: APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

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(X0) 15879377: MULTI-GPU FRAME RENDERING

(A1) 20190206018: MULTI-GPU FRAME RENDERING

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(X0) 15857330: MULTI-GPU FRAME RENDERING

(A1) 20190206023: MULTI-GPU FRAME RENDERING

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(X0) 14940067: LOW-LATENCY DISPLAY

(A1) 20170039926: LOW-LATENCY DISPLAY

(B2) 1: LOW-LATENCY DISPLAY

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(X0) 15176082: ARCHITECTURE AND ALGORITHMS FOR DATA COMPRESSION

(A1) 20170351429: ARCHITECTURE AND ALGORITHMS FOR DATA COMPRESSION

(B2) 1: ARCHITECTURE AND ALGORITHMS FOR DATA COMPRESSION

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(X0) 15826435: GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS

(A1) 20180321938: GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS

(B2) 1: GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS

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(X0) 15478176: GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

(A1) 20170205465: GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

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(X0) 16230929: IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS

(A1) 20190195947: IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS

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(X0) 13970547: BOUNDING VOLUME HIERARCHIES THROUGH TREELET RESTRUCTURING

(A1) 20140365532: BOUNDING VOLUME HIERARCHIES THROUGH TREELET RESTRUCTURING

(B2) 1: BOUNDING VOLUME HIERARCHIES THROUGH TREELET RESTRUCTURING

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(X0) 14979342: DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING

(A1) 20170178401: DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING

(B2) 1: DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING

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(X0) 15948886: PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM

(A1) 20180232332: PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM

(B2) 1: PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM

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(X0) 15993192: SAFE COMMUNICATION MODE FOR A HIGH SPEED LINK

(A1) 20180278278: SAFE COMMUNICATION MODE FOR A HIGH SPEED LINK

(B2) 1: SAFE COMMUNICATION MODE FOR A HIGH SPEED LINK

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(X0) 14979342: DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING

(A1) 20170178401: DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING

(B2) 1: DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING

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(X0) 16216720: Parallel Forward and Backward Propagation

(A1) 20190188569: Parallel Forward and Backward Propagation

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(X0) 14950134: OPTIMIZING MULTIPLE INVOCATIONS OF GRAPHICS PROCESSING UNIT PROGRAMS IN JAVA

(A1) 20170147299: OPTIMIZING MULTIPLE INVOCATIONS OF GRAPHICS PROCESSING UNIT PROGRAMS IN JAVA

(B2) 1: OPTIMIZING MULTIPLE INVOCATIONS OF GRAPHICS PROCESSING UNIT PROGRAMS IN JAVA

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(X0) 15881661: SYSTEM AND METHOD FOR REFERENCE NOISE COMPENSATION FOR SINGLE-ENDED SERIAL LINKS

(B1) 1: SYSTEM AND METHOD FOR REFERENCE NOISE COMPENSATION FOR SINGLE-ENDED SERIAL LINKS

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(X0) 15915975: FAULT DETECTION IN INSTRUCTION TRANSLATIONS

(A1) 20180260222: FAULT DETECTION IN INSTRUCTION TRANSLATIONS

(B2) 1: FAULT DETECTION IN INSTRUCTION TRANSLATIONS

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(X0) 15979547: SYSTEM AND METHOD FOR PROCEDURALLY SYNTHESIZING DATASETS OF OBJECTS OF INTEREST FOR TRAINING MACHINE-LEARNING MODELS

(A1) 20180260662: SYSTEM AND METHOD FOR PROCEDURALLY SYNTHESIZING DATASETS OF OBJECTS OF INTEREST FOR TRAINING MACHINE-LEARNING MODELS

(B2) 1: SYSTEM AND METHOD FOR PROCEDURALLY SYNTHESIZING DATASETS OF OBJECTS OF INTEREST FOR TRAINING MACHINE-LEARNING MODELS

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(X0) 15709397: UNIFIED MEMORY SYSTEMS AND METHODS

(A1) 20180018750: UNIFIED MEMORY SYSTEMS AND METHODS

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