SEARCH RESULTS for assignee:"mentor graphics"

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(X0) 16321929: Activity Coverage Assessment of Circuit Designs Under Test Stimuli

(A1) 20190179987: Activity Coverage Assessment of Circuit Designs Under Test Stimuli

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(X0) 16321929: Activity Coverage Assessment of Circuit Designs Under Test Stimuli

(A1) 20190179987: Activity Coverage Assessment of Circuit Designs Under Test Stimuli

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(X0) 16216127: PUZZLE-BASED PATTERN ANALYSIS AND CLASSIFICATION

(A1) 20190179996: PUZZLE-BASED PATTERN ANALYSIS AND CLASSIFICATION

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(X0) 14950947: EXECUTION OF COMPLEX RECURSIVE ALGORITHMS

(A1) 20160147516: EXECUTION OF COMPLEX RECURSIVE ALGORITHMS

(B2) 1: EXECUTION OF COMPLEX RECURSIVE ALGORITHMS

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(X0) 15287537: LOW-LEVEL SENSOR FUSION

(A1) 20180067489: LOW-LEVEL SENSOR FUSION

(B2) 1: LOW-LEVEL SENSOR FUSION

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(X0) 15592763: Wide-Range Clock Signal Generation For Speed Grading Of Logic Cores

(A1) 20170328952: Wide-Range Clock Signal Generation For Speed Grading Of Logic Cores

(B2) 1: Wide-Range Clock Signal Generation For Speed Grading Of Logic Cores

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(X0) 15873827: DYNAMIC DISTRIBUTED RESOURCE MANAGEMENT

(A1) 20190146847: DYNAMIC DISTRIBUTED RESOURCE MANAGEMENT

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(X0) 15084993: Guiding Patterns Optimization For Directed Self-Assembly

(A1) 20160292309: Guiding Patterns Optimization For Directed Self-Assembly

(B2) 1: Guiding Patterns Optimization For Directed Self-Assembly

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(X0) 15201291: PATTERN MATCHING USING EDGE-DRIVEN DISSECTED RECTANGLES

(A1) 20180004888: PATTERN MATCHING USING EDGE-DRIVEN DISSECTED RECTANGLES

(B2) 1: PATTERN MATCHING USING EDGE-DRIVEN DISSECTED RECTANGLES

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(X0) 15050447: Preserving Hierarchy And Coloring Uniformity In Multi-Patterning Layout Design

(A1) 20170242953: Preserving Hierarchy And Coloring Uniformity In Multi-Patterning Layout Design

(B2) 1: Preserving Hierarchy And Coloring Uniformity In Multi-Patterning Layout Design

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(X0) 15885142: COVERGROUP NETWORK ANALYSIS

(A1) 20190121932: COVERGROUP NETWORK ANALYSIS

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(X0) 16134020: Full Memory Logical Erase For Circuit Verification

(A1) 20190087522: Full Memory Logical Erase For Circuit Verification

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(X0) 16134020: Full Memory Logical Erase For Circuit Verification

(A1) 20190087522: Full Memory Logical Erase For Circuit Verification

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(X0) 16134020: Full Memory Logical Erase For Circuit Verification

(A1) 20190087522: Full Memory Logical Erase For Circuit Verification

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(X0) 16134020: Full Memory Logical Erase For Circuit Verification

(A1) 20190087522: Full Memory Logical Erase For Circuit Verification

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(X0) 16134020: Full Memory Logical Erase For Circuit Verification

(A1) 20190087522: Full Memory Logical Erase For Circuit Verification

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(X0) 16134020: Full Memory Logical Erase For Circuit Verification

(A1) 20190087522: Full Memory Logical Erase For Circuit Verification

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(X0) 13017788: LOGIC-DRIVEN LAYOUT VERIFICATION

(A1) 20110320990: LOGIC-DRIVEN LAYOUT VERIFICATION

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(X0) 16217956: VERIFICATION OF PHOTONIC INTEGRATED CIRCUITS

(A1) 20190114384: VERIFICATION OF PHOTONIC INTEGRATED CIRCUITS

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(X0) 15411839: ELECTROMIGRATION CHECK IN LAYOUT DESIGN USING COMPILED RULES LIBRARY

(A1) 20180210995: ELECTROMIGRATION CHECK IN LAYOUT DESIGN USING COMPILED RULES LIBRARY

(B2) 1: ELECTROMIGRATION CHECK IN LAYOUT DESIGN USING COMPILED RULES LIBRARY